System-Level Design of Networks-on-Chip for Heterogeneous Systems-on-Chip

Yoon, Young Jin; Mantovani, Paolo; Carloni, Luca P.

doi:10.1145/3130218.3130238

Cited by 8 publications

(2 citation statements)

References 17 publications

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“…Authors also propose mapping SNNs onto the target architecture. Authors argue that mesh-based NoCs that are used to interconnect cores in recent neuromorphic designs, have relatively long time-multiplexed connections that need to be near-continuously powered up and down, reaching from the ports of data producers/consumers (inside a core or between different cores) up to the ports of communication switches [127,128,129,125,130,131]. To address this, authors propose segmented bus.…”

Section: System Software For Performance and Energy Optimizationmentioning

confidence: 99%

Implementing Spiking Neural Networks on Neuromorphic Architectures: A Review

Huynh¹,

Varshika²,

Paul³

et al. 2022

Preprint

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Recently, both industry and academia have proposed several different neuromorphic systems to execute machine learning applications that are designed using Spiking Neural Networks (SNNs). With the growing complexity on design and technology fronts, programming such systems to admit and execute a machine learning application is becoming increasingly challenging. Additionally, neuromorphic systems are required to guarantee real-time performance, consume lower energy, and provide tolerance to logic and memory failures. Consequently, there is a clear need for system software frameworks that can implement machine learning applications on current and emerging neuromorphic systems, and simultaneously address performance, energy, and reliability. Here, we provide a comprehensive overview of such frameworks proposed for both, platform-based design and hardware-software co-design. We highlight challenges and opportunities that the future holds in the area of system software technology for neuromorphic computing.

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Section: System Software For Performance and Energy Optimizationmentioning

confidence: 99%

Implementing Spiking Neural Networks on Neuromorphic Architectures: A Review

Huynh¹,

Varshika²,

Paul³

et al. 2022

Preprint

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“…Currently, customizing the NoC topology is not automated in the ESP SoC integration flow. System architects, however, may explore different topologies by modifying the router instances and updating the logic to generate the header flit for the NoC packets [50].…”

Section: System Interconnectmentioning

confidence: 99%

Agile SoC Development with Open ESP

Mantovani,

Giri,

Di Guglielmo

et al. 2020

Preprint

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ESP is an open-source research platform for heterogeneous SoC design. The platform combines a modular tile-based architecture with a variety of application-oriented flows for the design and optimization of accelerators. The ESP architecture is highly scalable and strikes a balance between regularity and specialization. The companion methodology raises the level of abstraction to system-level design and enables an automated flow from software and hardware development to full-system prototyping on FPGA. For application developers, ESP offers domain-specific automated solutions to synthesize new accelerators for their software and to map complex workloads onto the SoC architecture. For hardware engineers, ESP offers automated solutions to integrate their accelerator designs into the complete SoC. Conceived as a heterogeneous integration platform and tested through years of teaching at Columbia University, ESP supports the open-source hardware community by providing a flexible platform for agile SoC development.

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