A Minimal Network Interface for a Simple Network-on-Chip

Schoeberl, Martin; Pezzarossa, Luca; Sparsø, Jens

doi:10.1007/978-3-030-18656-2_22

Cited by 7 publications

(6 citation statements)

References 14 publications

(21 reference statements)

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“…Owing to the ability of NoC to overcome the limitations of the conventional busbased system interconnects (e.g., unbearable increasing density and complexity induced by the system interconnect) [27], [30], [31], NoC is commonly used in the state-of-the-art multicore platforms. FIGURE 12 (a) shows the conventional NoC architecture, and the processor core in the platform communicates with other IPs only through the dedicated network interface (NI) of NoC [28], [32]. Therefore, since the developed TCU operates independently between the core and the network, if it is embedded in NI, TC can be realized on the platform no matter what cores are used.…”

Section: Expansion Of Tc Capability a Embedding The Tcu Into Network-on-chipmentioning

confidence: 99%

Developing a Multicore Platform Utilizing Open RISC-V Cores

et al. 2021

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RISC-V has been experiencing explosive growth since its first appearance in 2011. Dozens of free and open cores developed based on this instruction set architecture have been released, and RISC-V based devices optimized for specific applications such as the IoT and wearables, embedded systems, AI, and virtual, augmented reality are emerging. As the RISC-V cores are being used in various fields, the demand for multicore platforms composed of RISC-V cores is also rapidly increasing. Although there are various RISC-V cores developed for each specific application, and it seems possible to pick them up to create the most optimized multicore for the target application, unfortunately it is very difficult to realize this in reality. This is mainly because most open cores are released in the form of a single core without cache coherence logic, which requires expensive design effort and development costs to address it. To tackle this issue, this paper proposes a method to solve the cache coherence problem without additional effort from the developer and to maximize the performance of the multicore composed of the RISC-V core selected by the developer. Along with a description of the sophisticated operating mechanisms of the proposed method, this paper details the architecture and hardware implementation of the proposed method. Experiments conducted through the prototype development of a RISC-V multicore platform involving the proposed architecture and development of an application running on the platform demonstrate the effectiveness of the proposed method.INDEX TERMS Multicore platform, RISC-V, system-on-chip (SoC), electronic design automation (EDA)

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Section: Expansion Of Tc Capability a Embedding The Tcu Into Network-on-chipmentioning

confidence: 99%

Developing a Multicore Platform Utilizing Open RISC-V Cores

et al. 2021

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“…In contrast, the Argo NoC [17] uses TDM for the arbitration in the routers and at the NI [42], resulting in an end-to-end TDM schedule. S4NOC [37,36] is a TDM based NoC, simpler than Argo, with FIFO buffers as NI. We use S4NOC in the evaluation section.…”

Section: Network-on-chipmentioning

confidence: 99%

“…We have implemented a distributed shared memory in the T-CREST multicore [29]. We use two instances of the S4NOC [36]: one is used to write to a remote SPM or transmit a read request, and the second is used to return the read result. The SPMs are mapped into different address ranges in the global address range, and the read or write address determines which SPM to access.…”

Section: Distributed Shared On-chip Memorymentioning

confidence: 99%

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Multicore Models of Communication for Cyber-Physical Systems

Schoeberl

2020

Cyber Physical Systems. Model-Based Design

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Cyber-physical systems are systems where the environment interacts with computers (the cyber part) with real-time constraints. Emerging technologies, such as artificial intelligence and machine learning, call for ever-increasing processing power. However, for real-time systems, we need to prove statically that this processing demand can be performed within strict deadlines. This paper explores a time-predictable multicore architecture for those demanding cyber-physical systems. We explore different models of communication between those multiple cores. We compare the message passing model on top of a network-on-chip with message passing on two forms of shared scratchpad memory.

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“…Only recently, a minimal network interface for S4NOC [17] was published that is very similar to PIMP. It also uses a send and receive FIFO and polling to avoid overflows.…”

Section: Interface For Short Messagesmentioning

confidence: 99%

PIMP My Many-Core: Pipeline-Integrated Message Passing

Mische

Frieb

Stegmeier

et al. 2019

Lecture Notes in Computer Science

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To improve the scalability, several many-core architectures use message passing instead of shared memory accesses for communication. Unfortunately, Direct Memory Access (DMA) transfers in a shared address space are usually used to emulate message passing, which entails a lot of overhead and thwarts the advantages of message passing. Recently proposed register-level message passing alternatives use special instructions to send the contents of a single register to another core. The reduced communication overhead and architectural simplicity lead to good many-core scalability. After investigating several other approaches in terms of hardware complexity and throughput overhead, we recommend a small instruction set extension to enable register-level message passing at minimal hardware costs and describe its integration into a classical five stage RISC-V pipeline.

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A Minimal Network Interface for a Simple Network-on-Chip

Cited by 7 publications

References 14 publications

Developing a Multicore Platform Utilizing Open RISC-V Cores

Developing a Multicore Platform Utilizing Open RISC-V Cores

Multicore Models of Communication for Cyber-Physical Systems

PIMP My Many-Core: Pipeline-Integrated Message Passing

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