Recent advancements in technology scaling have sparked a trend towards greater integration with large-scale chips containing thousands of processors connected to memories and other I/O devices using non-trivial network topologies. Software simulation suffers from long execution times or reduced accuracy in such complex systems, whereas hardware RTL development is too time-consuming. We present OpenSoC Fabric, a parameterizable and powerful on-chip network generator for evaluating future large-scape chip multiprocessors and SoCs. OpenSoC Fabric leverages a new hardware DSL, Chisel, which contains powerful abstractions provided by its base language, Scala, and generates both software (C++) and hardware (Verilog) models from a single code base. This is in contrast to other tools readily available which typically provide either software or hardware models, but not both. The OpenSoC Fabric infrastructure is modeled after existing state-of-the-art simulators, offers large and powerful collections of configuration options, is open-source, and uses object-oriented design and functional programming to make functionality extension as easy as possible.
A cache-coherent memory subsystem plays an important role in complex digital computing systems. It maintains memory consistency across on-chip caches that hide the memory latency to improve computational performance. Being managed by hardware, the cache subsystem facilitates multi-core system programming and allows developers to focus on other crucial aspects. However, due to extensive protocol-related traffic and lack of explicit data movement management, cache memory scalability becomes a big concern. Existing evaluation techniques, such as cycle-approximate estimation or cycle-accurate simulation, do not guarantee accurate and fast results in the first case or require tremendous amount of efforts to implement and modify the system in the second. We present Open Cache Coherence (Open2C). The project aims to provide a powerful yet flexible and easy-to-extend tool that enables exploring coherent cache memory subsystem for upcoming large-scale computing systems. Open2C includes a library of basic parameterized components that are required to build a complex coherent cache memory subsystem, such as miss register, TAG array, replacement policy unit, etc. The Open2C generator is written in Chisel language that allows each component to be accessed through provided methods in a functional and modular way. The generated system can be simulated using existing Chisel-based simulation tools or be compiled into the RTL and placed on FPGA for further evaluation. Open2C reduces the amount of effort researches spend on system implementation-allowing them to focus on the protocol itself or a separate unit optimization. CCS CONCEPTS • Computer systems organization → Architectures; • Computing methodologies → Modeling and simulation; • Hardware ACM acknowledges that this contribution was authored or co-authored by an employee, contractor, or affiliate of the United States government. As such, the United States government retains a nonexclusive, royalty-free right to publish or reproduce this article, or to allow others to do so, for government purposes only.
scite is a Brooklyn-based organization that helps researchers better discover and understand research articles through Smart Citations–citations that display the context of the citation and describe whether the article provides supporting or contrasting evidence. scite is used by students and researchers from around the world and is funded in part by the National Science Foundation and the National Institute on Drug Abuse of the National Institutes of Health.