Characterizing the Performance of Hybrid Memory Cube Using ApexMAP Application Probes

Ibrahim, Khaled Z.; Fatollahi-Fard, Farzad; Donofrio, David; Shalf, John

doi:10.1145/2989081.2989090

Cited by 5 publications

(3 citation statements)

References 17 publications

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“…Previous works have characterized the HMC [15]- [17], [29], from which Schmidt et al [16] agreed with our measured bandwidth and latency. Another work, [18], using the AC-510 accelerator board, characterized bandwidth of HMC and its relationship with temperature, power, and cooling power.…”

Section: Related Worksupporting

confidence: 91%

Performance Implications of NoCs on 3D-Stacked Memories: Insights from the Hybrid Memory Cube

Hadidi

Asgari

Young

et al. 2018

2018 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS)

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Three-dimensional (3D)-stacked memories, such as Hybrid Memory Cube (HMC), provide a promising solution for overcoming the bandwidth wall between processors and memory by integrating memory and logic dies in a single stack. Such memories also utilize a network-on-chip (NoC) to connect their internal structural elements and to enable scalability. This novel usage of NoCs enables numerous benefits such as high bandwidth and memory-level parallelism and creates future possibilities for efficient processing-in-memory techniques. However, the implications of such NoC integration on the performance characteristics of 3D-stacked memories in terms of memory access latency and bandwidth have not been fully explored. This paper addresses this knowledge gap (i) by characterizing an HMC prototype using Micron's AC-510 accelerator board and by revealing its access latency and bandwidth behaviors; and (ii) by investigating the implications of such behaviors on system and software designs. Compared to traditional DDR-based memories, our examinations reveal the performance impacts of NoCs for current and future 3D-stacked memories and demonstrate how the packet-based protocol, internal queuing characteristics, traffic conditions, and other unique features of the HMC affects performance of applications.

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Section: Related Worksupporting

confidence: 91%

Performance Implications of NoCs on 3D-Stacked Memories: Insights from the Hybrid Memory Cube

Hadidi

Asgari

Young

et al. 2018

2018 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS)

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show abstract

“…However, for less than 53% read ratio, a total read latency of 192 ns and 224 ns (for 12.5 and 10 Gpbs respectively) is reported. Also, the power consumption, measured in that paper is up to 9 W. In another experimental paper, Ibrahim et al [10] analyzed the effect of spatial and temporal locality of accesses to HMC on its throughput with an EX800 backplane consisting of four Stratix FPGAs. They emphasized that access patterns with high temporal and spatial locality can operate up to 20 times as fast as other applications.…”

Section: E Latency Experimentsmentioning

confidence: 89%

“…Part#: xcku060-ffva1156-2-e 8 For all experiments, after 200 seconds, temperature is stable 9. To display the heat island created by HMC, we modify the heat scale, also shown at the right of each image 10. These fans are for cooling only the backplane and not the machine.…”

mentioning

confidence: 99%

Demystifying the characteristics of 3D-stacked memories: A case study for Hybrid Memory Cube

Hadidi

Asgari

Mudassar

et al. 2017

2017 IEEE International Symposium on Workload Characterization (IISWC)

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Abstract-Three-dimensional (3D)-stacking technology, which enables the integration of DRAM and logic dies, offers high bandwidth and low energy consumption. This technology also empowers new memory designs for executing tasks not traditionally associated with memories. A practical 3D-stacked memory is Hybrid Memory Cube (HMC), which provides significant access bandwidth and low power consumption in a small area. Although several studies have taken advantage of the novel architecture of HMC, its characteristics in terms of latency and bandwidth or their correlation with temperature and power consumption have not been fully explored. This paper is the first, to the best of our knowledge, to characterize the thermal behavior of HMC in a real environment using the AC-510 accelerator and to identify temperature as a new limitation for this state-ofthe-art design space. Moreover, besides bandwidth studies, we deconstruct factors that contribute to latency and reveal their sources for high-and low-load accesses. The results of this paper demonstrates essential behaviors and performance bottlenecks for future explorations of packet-switched and 3D-stacked memories.

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The Future of High Performance Computing in Biomimetics and Some Challenges

Fernandes,

Kharate,

Singh

2024

High Performance Computing in Biomimetics

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Characterizing the Performance of Hybrid Memory Cube Using ApexMAP Application Probes

Cited by 5 publications

References 17 publications

Performance Implications of NoCs on 3D-Stacked Memories: Insights from the Hybrid Memory Cube

Performance Implications of NoCs on 3D-Stacked Memories: Insights from the Hybrid Memory Cube

Demystifying the characteristics of 3D-stacked memories: A case study for Hybrid Memory Cube

The Future of High Performance Computing in Biomimetics and Some Challenges

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