Demystifying the characteristics of 3D-stacked memories: A case study for Hybrid Memory Cube

Hadidi, Ramyad; Asgari, Bahar; Mudassar, Burhan Ahmad; Mukhopadhyay, Saibal; Yalamanchili, Sudhakar; Kim, Hyesoon

doi:10.1109/iiswc.2017.8167757

Cited by 51 publications

(29 citation statements)

References 16 publications

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“…For instance, let the system have a lookup table for IP addresses lookup, where table entry of each IP address is allocated in a flat manner so that every lookup for a packet finishes with one memory access. Typical latency of single memory access to HMC is usually between 100-180 [ns] with an average of 125 [ns], according to [68], [69]. Thus we assume that the service rate of the 3D-stacked DRAM, µ, is 8 M services per second.…”

Section: Numerical Simulation Resultsmentioning

confidence: 99%

Packet Processing Architecture Using Last-Level-Cache Slices and Interleaved 3D-Stacked DRAM

Korikawa

Kawabata

et al. 2020

IEEE Access

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Packet processing performance of Network Function Virtualization (NFV)-aware environment depends on the memory access performance of commercial-off-the-shelf (COTS) hardware systems. Table lookup is a typical example of packet processing, which has a significant dependence on memory access performance. Thus, the on-chip cache memories of the CPU are becoming more and more critical for many high-performance software routers or switches. Moreover, in the carrier network, multiple applications run on top of the same hardware system in parallel, which requires the capacity of cache memories. In this paper, we propose a packet processing architecture that enhances memory access parallelism by combining on-chip last-level-cache (LLC) slices and off-chip interleaved 3 Dimensional (3D)-stacked Dynamic Random Access Memory (DRAM) devices. Table entries are stored in the off-chip 3D-stacked DRAM, so that memory requests are processed in parallel by using bank interleaving and channel parallelism. Also, cached entries are distributed to on-chip LLC slices according to a memory address-based hash function so that each CPU core can access on-chip LLC in parallel. The evaluation results show that the proposed architecture reduces the memory access latency by 62 % and 12 % and increases the throughput by 108 % and 2 % with reducing blocking probability of memory requests 96 % and 50 %, compared to the architecture with on-chip shared LLC and that without on-chip LLC, respectively.

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Section: Numerical Simulation Resultsmentioning

confidence: 99%

Packet Processing Architecture Using Last-Level-Cache Slices and Interleaved 3D-Stacked DRAM

Korikawa

Kawabata

et al. 2020

IEEE Access

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“…For example, let service rate µ be 8 M services per second, which is an estimate since typical latency inside the HMC itself is usually taken to be between 100-180 ns with average of 125 ns [27], [28], and let the traffic load be 1.2. Table 6 lists the calculation results of M/M/S/K, proposed architecture with Poisson arrival, and that with IPP arrival.…”

Section: Packet Processing Performancementioning

confidence: 99%

Carrier-Scale Packet Processing Architecture Using Interleaved 3D-Stacked DRAM and Its Analysis

Korikawa

Kawabata

et al. 2019

IEEE Access

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New network services such as the Internet of Things and edge computing are accelerating the increase in traffic volume, the number of connected devices, and the diversity of communication. Next generation carrier network infrastructure should be much more scalable and adaptive to rapid increase and divergence in network demand with much lower cost. A more virtualization-aware, flexible and inexpensive system based on general-purpose hardware is necessary to transform the traditional carrier network into a more adaptive, next generation network. In this paper, we propose an architecture for carrierscale packet processing that is based on interleaved 3 dimensional (3D)-stacked dynamic random access memory (DRAM) devices. The proposed architecture enhances memory access concurrency by leveraging vault-level parallelism and bank interleaving of 3D-stacked DRAM. The proposed architecture uses the hash-function-based distribution of memory requests to each set of vault and bank; a significant portion of the full carrier-scale tables. We introduce an analytical model of the proposed architecture for two traffic patterns; one with random memory request arrivals and one with bursty arrivals. By using the model, we calculate the performance of a typical Internet protocol routing application as a benchmark of carrier-scale packet processing wherein main memory accesses are inevitable. The evaluation shows that the proposed architecture achieves around 80 Gbps for carrier-scale packet processing involving both random and bursty request arrivals.

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“…Note that monitoring logic measures aggregate latencies of the HMC controller, transceiver, data transmission on links, internal NoC, TSV transmission, and DRAM timings. Detailed studies of these latencies are performed in [18], upon which we build our new measurements.…”

Section: B Firmware and Softwarementioning

confidence: 99%

“…The number of active ports is a proxy for the requested bandwidth because it has a direct relationship with the number of issued requests with the GUPS implementation. Figure 13 HMC characterization also mentioned [18], the factor that limits the bandwidth utilization can be related to packetswitched network, such as the limited size of queues in the vault controller or DRAM layers. We analyze the reasons of saturation points by taking a deeper look at a vault controller, which is basically a stationary system, receiving requests with an arrival rate.…”

Section: F Requested and Response Bandwidth Analysismentioning

confidence: 99%

Performance Implications of NoCs on 3D-Stacked Memories: Insights from the Hybrid Memory Cube

Hadidi

Asgari

Young

et al. 2018

2018 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS)

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Three-dimensional (3D)-stacked memories, such as Hybrid Memory Cube (HMC), provide a promising solution for overcoming the bandwidth wall between processors and memory by integrating memory and logic dies in a single stack. Such memories also utilize a network-on-chip (NoC) to connect their internal structural elements and to enable scalability. This novel usage of NoCs enables numerous benefits such as high bandwidth and memory-level parallelism and creates future possibilities for efficient processing-in-memory techniques. However, the implications of such NoC integration on the performance characteristics of 3D-stacked memories in terms of memory access latency and bandwidth have not been fully explored. This paper addresses this knowledge gap (i) by characterizing an HMC prototype using Micron's AC-510 accelerator board and by revealing its access latency and bandwidth behaviors; and (ii) by investigating the implications of such behaviors on system and software designs. Compared to traditional DDR-based memories, our examinations reveal the performance impacts of NoCs for current and future 3D-stacked memories and demonstrate how the packet-based protocol, internal queuing characteristics, traffic conditions, and other unique features of the HMC affects performance of applications.

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Demystifying the characteristics of 3D-stacked memories: A case study for Hybrid Memory Cube

Cited by 51 publications

References 16 publications

Packet Processing Architecture Using Last-Level-Cache Slices and Interleaved 3D-Stacked DRAM

Packet Processing Architecture Using Last-Level-Cache Slices and Interleaved 3D-Stacked DRAM

Carrier-Scale Packet Processing Architecture Using Interleaved 3D-Stacked DRAM and Its Analysis

Performance Implications of NoCs on 3D-Stacked Memories: Insights from the Hybrid Memory Cube

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