ONO inter-poly dielectric scaling for nonvolatile memory applications

Multi-layer high-κ interpoly dielectric for floating gate flash memory devices

“…However, decreasing the thickness of the IPD to increase the floating gate capacitance may cause serious leakage and reliability problems which are fatal in the retention time of flash memories. Although many studies have been done on this issue, current ONO stack starts failing in the 10-12 nm range because of excessive leakage current [3,4]. The use of high-j dielectric materials in the IPD layer is a very attractive option because it combines 0038-1101/$ -see front matter Ó 2008 Elsevier Ltd. All rights reserved.…”

Effect of electric field polarity on inter-poly dielectric during cell operation for the retention characteristics

“…Then, when the positive bias was applied, the electric field of the top oxide was enhanced by the charges trapped from the previous sweep, since the direction of the band bending for the ONO stack was reversed as shown in Fig. 5 and the leakage current at moderate electric field was related to the hole current of the top oxide [15]. The reduction of the leakage current of sweep C in Fig.…”

High performance sub-0.25 /spl mu/m devices using ultrathin oxide-nitride-oxide gate dielectric formed with low pressure oxidation and chemical vapor deposition

“…The ONO gate stack was formed in four major process steps: after a conventional pre-gate oxide clean, the silicon surface was first oxidized in oxygen at a pressure of 800 mtorr and a temperature of 750 C to form an oxide thickness of 10 Å. Twenty Å of silicon nitride was then deposited on the oxidized layer at a pressure of 100 mtorr and a temperature of 800 C using dichlorosilane and ammonia as deposition precursors. To establish an electrical contact with poly-si electrode [9] and suppress gate leakage current [17], the dual layer was then topped with a 10 Å Tetraethoxysilane (TEOS) oxide deposited at a pressure of 450 mtorr and a temperature of 700 C. The TEOS oxide is needed to suppress gate leakage current. The whole ONO stack was then in-situ densified in N O gases at the TEOS deposition temperature and then ex-situ annealed with a rapid thermal process (900 C for 30 s in nitrogen) which reduces SiO /Si interfacial defect density and fixed charge density [11].…”

“…In this letter, we report a new approach to processing ONO resulting in highly reliable, high performance gate dielectrics. Compared to a single layer of SiO , the ONO stacked gate dielectric has 1) a low SiO /Si interface trap density [11]; 2) a higher effective dielectric constant; 3) a higher dielectric breakdown field [9], [12]; 4) a low leakage current at low field [14]; and 5) a better barrier against boron penetration to device channels from boron doped poly-silicon [15]. Most recently, it has been demonstrated that a 8 Å layer of nitride is sufficient to stop boron penetration [16].…”