Multi-layer high-κ interpoly dielectric for floating gate flash memory devices

Technique to improve performance of Al2O3 interpoly dielectric using a La2O3 interface scavenging layer for floating gate memory structures

“…1͒. In the absence of any IL, significant leakage reduction was observed ͑ϳ3 orders͒, which is in similar agreement with the findings of Lu et al 3 However, all stacks showed similar gate injection leakages at high voltages ͑F-N dominating͒ as the gate electrode-dielectric interfaces are the same.…”

“…2 However, in spite of the good properties of Al 2 O 3 , its full potential has not been realized due to the presence of an SiO 2 ͑low-͒ interface that typically grows at the interface between the polysilicon floating gate and IPD. It has been reported that this interfacial layer ͑IL͒ can significantly increase the leakage at moderately large voltages 3 due to the band offset that exists between the SiO 2 and Al 2 O 3 . This can potentially degrade the retention characteristics of the memory device.…”

“…Since the band offset results from the different band gaps ͑E g ͒ of the IL and the IPD, having a high-/low-͑i.e., low-E g /high-E g ͒ barrier near the substrate ͑higher close to substrate͒ is expected to result in better leakage compared to a low-/high-barrier. 3,4 Therefore, the removal of the low-SiO 2 or its replacement with a higher-material is critical in improving the leakage characteristics of Al 2 O 3 IPD stacks.…”

YAlO

“…The curves of the Al203 and l-A1203 samples exhibit obvious frequency dispersion, and their C-V curves measured at 50 kHz show a bump in the transition region, indicating their bad dielectric qualities. For the AI203 sample, this should be due to large number of interfacial defects existing in the poor interface layer between the AI203 and Si substrate [3][4]. It also indicates that the Y content in the 1-Y AIO sample may be not enough to scavenge the poor interfacial layer so that it also presents lots of interface states.…”

“…Among various high-k dielectrics, Ab03 seems to be a promising candidate due to its large band-gap (� 8.8 eV, which is only next to the value of Si02) and higher k value (�9) than Si02 (�3.9) [1-2]. However, the formation of a poor low-k Si02 interfacial layer between Ab03 and floating gate (poly-Si) is unavoidable during the AI203 deposition which may increase the leakage and degrade the flash memory's quality [3][4]. In order to remove the interfacial layer, Jayanti et at.…”