High performance sub-0.25 /spl mu/m devices using ultrathin oxide-nitride-oxide gate dielectric formed with low pressure oxidation and chemical vapor deposition

Abstract

An ultra-thin, high reliability oxide-nitride-oxide (ONO) gate dielectric was formed using low pressure oxidation and chemical vapor deposition. A sub-0.25 m device with high performance was fabricated whose gate dielectric reliability was studied using both Fowler-Nordheim tunneling stress and hot carrier aging. The results from both techniques demonstrate that the device lifetime is longer than 100 years. Auger spectroscopy shows that there is about 9 atomic % nitrogen at the SiO 2 /Si interface. However, no transconductance degradation is observed.

Nitrogen diffusion and accumulation at the Si∕SiO2 interface in SiO2∕Si3N4∕SiO2 structures for nonvolatile semiconductor memories

“…1,2 Memory effect is connected with trapping of electrons and holes at deep traps in the silicon nitride layer of ONO. [3][4][5][6][7][8][9][10][11][12][13][14] In this work we attempt to resolve this controversy through a specially designed set of experiments aimed to distinguish between different factors influencing nitrogen spatial distribution in ONO stacks. Degradation effects are much less pronounced for ONO with nitrided BOX.…”

“…4,5 Thermal nitridation of silicon oxide also showed nitrogen bonding at the Si/ SiO 2 interface. 4,5 Thermal nitridation of silicon oxide also showed nitrogen bonding at the Si/ SiO 2 interface.…”

Advanced Gate Dielectric Development for VLSI Technology

“…High performance devices with gate dielectric EOT of 30 Å have been fabricated in a similar approach where the nitride layer was formed with a low pressure chemical vapor deposition (LPCVD) process instead [10]. As shown in Fig.…”

Impacts of Buffer Oxide Layer in Nitride/Oxide Stack Gate Dielectrics on the Device Performance and Dielectric Reliability

“…However, the integration of high-K materials generally requires an interfacial buffer oxide to maintain good interface quality, improve reliability, and prevent chemical reaction with Si. [2][3][4][5][6][7][8] Incorporation of such interfacial oxide can significantly lower the overall dielectric constant and results in severe limitation on the scalability of high-K gate dielectrics. Therefore, it is crucial to determine the suitable thickness of interfacial oxide judged from leakage current, device performance, and dielectric reliability.…”

“…On the other hand, silicon nitride has been an attractive option for replacement of SiO 2 in the near future due to simple process integration and excellent barrier property. [2][3][4] Like most of the high-K gate materials, an interfacial buffer oxide is required to preserve interface quality for successful integration of Si 3 N 4 gate dielectric. [2][3][4] In this work, we have investigated the impacts of the buffer layer in the nitride/oxide ͑N/O͒ gate stack on the device performance and dielectric reliability, in which the ultrathin buffer oxide was realized by in situ H 2 (2%)/O 2 anneal of the chemical vapor deposited Si 3 N 4 layer.…”