On the Trap Locations in Bulk FinFETs After Hot Carrier Degradation (HCD)

Yu, Zhuoqing; Zhang, Zhe; Sun, Zixuan; Wang, Runsheng; Huang, Ru

doi:10.1109/ted.2020.2994171

Cited by 29 publications

(16 citation statements)

References 28 publications

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“…From the trap-based research in HCD, both interface and oxide traps contribute to the overall degradation [ 5 ]. A modified compact model and trap spatial distribution investigations facilitate the accurate characterization of HCD [ 6 , 7 , 8 ]. To characterize the trap generation during HCD stress, a discharge-based multi-pulse technique (DMP) was introduced, which is accessible to oxide traps within and beyond the bandgap [ 9 , 10 ].…”

Section: Introductionmentioning

confidence: 99%

Insight into over Repair of Hot Carrier Degradation by GIDL Current in Si p-FinFETs Using Ultra-Fast Measurement Technique

Chang

Wang²,

Yang

et al. 2023

Nanomaterials

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In this article, an experimental study on the gate-induced drain leakage (GIDL) current repairing worst hot carrier degradation (HCD) in Si p-FinFETs is investigated with the aid of an ultra-fast measurement (UFM) technique (~30 μs). It is found that increasing GIDL bias from 3 V to 4 V achieves a 114.7% VT recovery ratio from HCD. This over-repair phenomenon of HCD by UFM GIDL is deeply discussed through oxide trap behaviors. When the applied gate-to-drain GIDL bias reaches 4 V, a significant electron trapping and interface trap generation of the fresh device with GIDL repair is observed, which greatly contributes to the approximate 114.7% over-repair VT ratio of the device under worst HCD stress (−2.0 V, 200 s). Based on the TCAD simulation results, the increase in the vertical electric field on the surface of the channel oxide layer is the direct cause of an extraordinary electron trapping effect accompanied by the over-repair phenomenon. Under a high positive electric field, a part of channel electrons is captured by oxide traps in the gate dielectric, leading to further VT recovery. Through the discharge-based multi-pulse (DMP) technique, the energy distribution of oxide traps after GIDL recovery is obtained. It is found that over-repair results in a 34% increment in oxide traps around the conduction energy band (Ec) of silicon, which corresponds to a higher stabilized VT shift under multi-cycle HCD-GIDL tests. The results provide a trap-based understanding of the transistor repairing technique, which could provide guidance for the reliable long-term operation of ICs.

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Section: Introductionmentioning

confidence: 99%

Insight into over Repair of Hot Carrier Degradation by GIDL Current in Si p-FinFETs Using Ultra-Fast Measurement Technique

Chang

Wang²,

Yang

et al. 2023

Nanomaterials

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“…In 2017, Jiang et al proposed an analytical model to capture the temperature of transistors in a digital circuit that is biased under pulse trains characterized by frequency and power duty cycle, then HCI performance is predicted [28]. Yu et al proposed a trap-based compact model [29][30][31], which can accurately predict hot carrier degradation and variation in full V gs /V ds bias. In 2019, a SPICE compatible compact hot carrier degradation time kinetics model was proposed for conventional, lightly doped drain, and drain extended MOSFETs and FinFETs [32].…”

Section: Introductionmentioning

confidence: 99%

“…The oxide traps generated in planar devices only have one type [29]. The difference can be explained in that FinFET has one more lattice orientation than the planar device [30]. The interface traps and oxide traps (type 1) are mainly located at the channel center closer to the source on the Fin sidewall, while the oxide traps (type 2) are mainly distributed at the channel center closer to the drain on the Fin top [30].…”

Section: Introductionmentioning

confidence: 99%

Hot Carrier Injection Reliability in Nanoscale Field Effect Transistors: Modeling and Simulation Methods

Wang

Yang³

et al. 2022

Electronics

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Hot carrier injection (HCI) can generate interface traps or oxide traps mainly by dissociating the Si-H or Si-O bond, thus affecting device performances such as threshold voltage and saturation current. It is one of the most significant reliability issues for devices and circuits. Particularly, the increase in heat generation per unit volume due to high integration density of advanced integrated circuits leads to a severe self-heating effect (SHE) of nanoscale field effect transistors (FETs), and low thermal conductivity of materials in nanoscale FETs further aggravates the SHE. High temperature improves the HCI reliability in the conventional MOSFET with long channels in which the energy of carriers can be relaxed. However, high temperature due to severe SHE deteriorates HCI reliability in nanoscale FETs, which is a big concern in device and circuit design. In this paper, the modeling and simulation methods of HCI in FETs are reviewed. Particularly, some recently proposed HCI models with consideration of the SHE are reviewed and discussed in detail.

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“…More recently, other lateral defect profiling techniques were developed to extract DPs induced by hotcarriers (HCs) from an I d -V d (Mamy Randriamihaja et al [11] and Wang et al [12]) or multiple I d -V g s (Yun et al [13]). Exploiting the information in time-dependent variability, Yu et al [14] identified typical locations of different HC-induced traps in finFETs, both along the device width (position in the top or side wall of the fin) as well as along the lateral channel direction.…”

Section: Introductionmentioning

confidence: 99%

The properties, effect and extraction of localized defect profiles from degraded FET characteristics

Vandemaele

Kaczer

Tyaginov

et al. 2021

2021 IEEE International Reliability Physics Symposium (IRPS)

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We report simulations of localized defect profiles (DPs), typical for hot-carrier degradation (HCD), with exponential-and step-like shapes. First, we analyze how these localized DPs affect the transistor I-V and model the complex relation between DP and FET degradation by considering the degraded FET as a series circuit of an undegraded transistor (the source side) and a degraded one (the drain side). We also compare how the same DP causes different degradation for changes in the device structure. Second, we use the DP simulations to qualitatively understand the DP dependence on stress voltages in measured FETs and assess how uniquely a DP can be extracted from degraded I-V metrics. The results are of interest for HCD modeling.

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On the Trap Locations in Bulk FinFETs After Hot Carrier Degradation (HCD)

Cited by 29 publications

References 28 publications

Insight into over Repair of Hot Carrier Degradation by GIDL Current in Si p-FinFETs Using Ultra-Fast Measurement Technique

Insight into over Repair of Hot Carrier Degradation by GIDL Current in Si p-FinFETs Using Ultra-Fast Measurement Technique

Hot Carrier Injection Reliability in Nanoscale Field Effect Transistors: Modeling and Simulation Methods

The properties, effect and extraction of localized defect profiles from degraded FET characteristics

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