The properties, effect and extraction of localized defect profiles from degraded FET characteristics

Vandemaele, Michiel; Kaczer, B.; Tyaginov, Stanislav; Franco, J.; Degraeve, R.; Chasin, Adrian; Wu, Z.; Bury, E.; Yang, Xiudi; Mertens, Hans; Groeseneken, G.

doi:10.1109/irps46558.2021.9405164

Cited by 3 publications

(1 citation statement)

References 23 publications

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“…However, the rapid downscaling of CMOS technologies, where supply voltages do not scale linearly with device dimensions, results in a concerning increase of IC degradation due to high electric fields that progressively, but inevitably, worsen IC projected reliability and lifetime [ 8 , 9 ]. In this scenario, IC degradation can lead circuits to progressive performance degradation or even critical failure caused by two of the major transistor aging mechanisms: bias temperature instability (BTI) [ 10 , 11 , 12 ] and hot carrier degradation (HCD) [ 13 , 14 , 15 , 16 ].…”

Section: Introductionmentioning

confidence: 99%

An In-Depth Study of Ring Oscillator Reliability under Accelerated Degradation and Annealing to Unveil Integrated Circuit Usage

Diaz-Fortuny,

Saraza-Canflanca,

Bury

et al. 2024

Micromachines

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The reliability and durability of integrated circuits (ICs), present in almost every electronic system, from consumer electronics to the automotive or aerospace industries, have been and will continue to be critical concerns for IC chip makers, especially in scaled nanometer technologies. In this context, ICs are expected to deliver optimal performance and reliability throughout their projected lifetime. However, real-time reliability assessment and remaining lifetime projections during in-field IC operation remain unknown due to the absence of trustworthy on-chip reliability monitors. The integration of such on-chip monitors has recently gained significant importance because they can provide real-time IC reliability extraction by exploiting the fundamental physics of two of the major reliability degradation phenomena: bias temperature instability (BTI) and hot carrier degradation (HCD). In this work, we present an extensive study of ring oscillator (RO)-based degradation and annealing monitors designed on our latest 28 nm versatile array chip. This test vehicle, along with a dedicated test setup, enabled the reliable statistical characterization of BTI- and HCD-stressed as well as annealed RO monitor circuits. The versatility of the test vehicle presented in this work permits the execution of accelerated degradation tests together with annealing experiments conducted on RO-based reliability monitor circuits. From these experiments, we have constructed precise annealing maps that provide detailed insights into the annealing behavior of our monitors as a function of temperature and time, ultimately revealing the usage history of the IC.

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Section: Introductionmentioning

confidence: 99%

An In-Depth Study of Ring Oscillator Reliability under Accelerated Degradation and Annealing to Unveil Integrated Circuit Usage

Diaz-Fortuny,

Saraza-Canflanca,

Bury

et al. 2024

Micromachines

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Dedicated ICs for the Characterization of Variability and Aging Studies and their Use in Lightweight Security Applications : Invited paper

Diaz-Fortuny

Saraza-Canflanca

Vandemaele

et al. 2022

2022 IEEE Latin American Electron Devices Conference (LAEDC)

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Towards Complete Recovery of Circuit Degradation by Annealing With On-Chip Heaters

Diaz-Fortuny

Saraza-Canflanca

Lofrano

et al. 2023

IEEE Electron Device Lett.

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This work reports an on-chip heater structure fabricated in the Front End of Line (FEOL) on a versatile ring-oscillator (RO) array utilized to conduct statistical characterization of on-chip annealing of statically, i.e., Bias Temperature Instabilities (BTI), and dynamically, i.e., BTI-Hot Carrier Degradation (HCD), stressed ROs. The heater allows to reach local temperatures up to T = +300 • C in milliseconds. Accurate thermal modelling of the heater structure has been conducted demonstrating that the heat is homogenously distributed across the array area, resulting in a valuable tool for precise on-chip circuit anneal.Exploiting the on-chip heater features, sequential annealing tests with increasing duration have been conducted after accelerated degradation of RO circuits. Moreover, we report detailed relaxation maps that allow a thorough insight into the annealing behaviour of our circuits vs temperature and time. This can potentially be used to anneal ICs "on-line" to prolong their useful lifetime towards a more sustainable use.

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The properties, effect and extraction of localized defect profiles from degraded FET characteristics

Cited by 3 publications

References 23 publications

An In-Depth Study of Ring Oscillator Reliability under Accelerated Degradation and Annealing to Unveil Integrated Circuit Usage

An In-Depth Study of Ring Oscillator Reliability under Accelerated Degradation and Annealing to Unveil Integrated Circuit Usage

Dedicated ICs for the Characterization of Variability and Aging Studies and their Use in Lightweight Security Applications : Invited paper

Towards Complete Recovery of Circuit Degradation by Annealing With On-Chip Heaters

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