Towards Complete Recovery of Circuit Degradation by Annealing With On-Chip Heaters

Abstract

This work reports an on-chip heater structure fabricated in the Front End of Line (FEOL) on a versatile ring-oscillator (RO) array utilized to conduct statistical characterization of on-chip annealing of statically, i.e., Bias Temperature Instabilities (BTI), and dynamically, i.e., BTI-Hot Carrier Degradation (HCD), stressed ROs. The heater allows to reach local temperatures up to T = +300 • C in milliseconds. Accurate thermal modelling of the heater structure has been conducted demonstrating that the heat is homogenously distributed across the array area, resulting in a valuable tool for precise on-chip circuit anneal.Exploiting the on-chip heater features, sequential annealing tests with increasing duration have been conducted after accelerated degradation of RO circuits. Moreover, we report detailed relaxation maps that allow a thorough insight into the annealing behaviour of our circuits vs temperature and time. This can potentially be used to anneal ICs "on-line" to prolong their useful lifetime towards a more sustainable use.

An In-Depth Study of Ring Oscillator Reliability under Accelerated Degradation and Annealing to Unveil Integrated Circuit Usage

“…To efficiently use the 1 mm 2 area, the chip design incorporates a total of 6 individual submodules, each comprising 24 pads for both analog and digital operations. Consequently, the full die accumulates a total of 144 pads, each pad measuring 55 µm × 55 µm, including more than 600 degradation monitors [ 30 , 40 ] (see Figure 1 a). Each monitor is integrated into a block referred to as a ‘unit cell’, which contains the necessary digital and analog circuitry to operate each RO individually under different bias conditions.…”

“…The thermal model was used to investigate the temperature uniformity along the die and the impact of temperature variations since the heater stripes are placed 35 mm away from each other. In this regard, Figure 5 b reveals that the maximum temperature at, for instance, 0.6 W is 177 °C and the temperature variation among the heater strips do not exceed 1 °C [ 40 ].…”

“…Moreover, the heater structure allows for on-chip homogeneous and fast temperature setting of ∆T = +300 °C with setting times of approximately 1 s, a significantly faster temperature setting system when compared with commercial thermochucks or oven annealing [55,56]. The versatility of our FEOL heater allows us to execute logarithmic temperature tests where the annealing temperature is switched from 25 °C to, for instance, 325 °C for annealing experiments on our regular-and True-HCD aging monitors [40,55], as depicted in Figure 4. High-temperature annealing cycles with exponentially increasing times are applied to our RO-based aging monitors by means of our on-chip heater structure.…”

“…325 °C for annealing experiments on our regular-and True-HCD aging monitors [40,55], as depicted in Figure 4. High-temperature annealing cycles with exponentially increasing times are applied to our RO-based aging monitors by means of our on-chip heater structure.…”

“…These two monitors together comprise our non-intrusive on-chip degradation monitoring technology, where the understood degradation kinetics allow us to determine the degradation of the IC and detect fraudulent tampering. Moreover, we review (ii) an on-chip heater structure designed in the Front End of Line (FEOL) with N+ diffusion resistors that allows for the execution of fast and reliable on-chip temperature annealing experiments employed to characterize the annealing behavior of our technology [ 40 ]. Finally, we present an in-depth study of (iii) RO-based degradation and annealing behavior, comparing BTI-dominated regular-RO-based monitors and our True-HCD monitors, where the acquired annealing knowledge can be utilized during in-field applications to enhance the accuracy of the IC age and clearly detect fraudulent annealing of the IC.…”