On the generation of test patterns for multiple faults

Abstract

This paper presents a new method to generate test patterns for multiple stuck-at faults in combinational circuits. We assume the presence of all multiple faults of all multiplicities and we do not resort to their explicit enumeration: the target fault is a single component of possibly several multiple faults. New line and gate models are introduced to handle multiple fault effect propagation through the circuits. The method tries to generate test conditions that propagate the effect of the target fault to primary outputs. When these conditions are fulfilled, the input vector is a test for the target fault and it is guaranteed that all multiple faults of all multiplicities containing the target fault as component are also detected. The method uses similar techniques to those in the FAN and SOCRATES algorithms to guide the search part of the algorithm and includes several new heuristics to enhance the performance and fault detection capability. Experiments performed on the ISCAS'85 benchmark circuits show that test sets for multiple faults can be generated with high fault coverage and a reasonable increase in cost over test generation for single stuck-at faults.

Synthesis of multiple fault oriented test groups from single fault test sets

“…In some works, structural constraints and masking relations of single faults are exploited to analyze the detectability of multiple faults [3][4][5]. The problems of ATPG-based grading of self-checking properties and strong fault-secureness under the conditions of possible multiple faults are discussed in [6,7].…”

Multiple faults: modeling, simulation and test

“…Algorithms for generating tests for multiple stuck-at faults exist [1]. Programming of such algorithms will be useful if we were to change the test objective, because the technique considers all multiple-faults rather than targeting one or a few specified faults.…”