On implementation of embedded phosphorus-doped SiC stressors in SOI nMOSFETs

Ren, Zhibin; Pei, Guangsheng; Li, J.; Takalkar, R.; Chan, K.; Xia, Guoping; Zhu, Zhengmao; Madan, A.; Pinto, T.; Adam, Thomas; Miller, J. N.; Dube, Abhishek; Black, L.; Weijtmans, J.W.; Yang, Bin; Harley, E.; Chakravarti, A.; Kanarsky, T.; Pal, Rohit; Lauer, Isaac; Park, D.-G.; Sadana, D. K.

doi:10.1109/vlsit.2008.4588607

Cited by 10 publications

(7 citation statements)

References 1 publication

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“…With eSi:C stressor and neutral liner, the I on was enhanced by ~ 28%, which is much higher than the tensile liner effect, indicating eSi:C is a very effective stressor for thick-oxide long-channel nMOS transistors. Although eSi:C was demonstrated to be a very effective stressor for thick-oxide longchannel nMOS transistors shown above, its stress benefit was barely detectable for the state-of-the-art thin-oxide short-channel nMOS devices [4]. The origin of the response discrepancy to eSi:C stressor between "thick-oxide long-channel nMOS" and "thin-oxide short-channel nMOS" is still unclear and need further study.…”

Section: In Situ Phosphorus-doped Esi:cmentioning

confidence: 95%

“…Considering that the conventional tensile stress liner becomes less and less effective with gate-pitch scaling for future generation nMOS devices, embedded Si:C (eSi:C) stressor becomes a hot topic in recent years [1][2][3][4] owing to its potential to further enhance nMOS channel mobility and drive current beyond the scope of the conventional stressors, such as tensile stress liner (TL) and stress memorization technique (SMT). Among the techniques used to embed Si:C into nMOS source and drian (S/D), the epitaxial growth method [1,3,4] is gaining momentum over the solid phase epitaxy (SPE) approach [2]. The advantage of SPE lies in that it does not require new tools, and it is more compatible with conventional CMOS processing, therefore, it is more cost effective.…”

Section: Introductionmentioning

confidence: 99%

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Recent Progress and Challenges in Enabling Embedded Si:C Technology

Yang¹,

Ren²,

Takalkar³

et al. 2008

ECS Trans.

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This paper discusses the fundamental challenges and reports the recent progress in enabling embedded Si:C (eSi:C) nMOS source/drain stressor technology. A thick oxide (SiON, Toxgl ~ 26Aå) long channel (Lgate in the range of 80nm-110nm, gate-pitch =336nm) nMOS device was used as the main test structure to evaluate the impact of eSi:C stressor to the device electrical characteristics, such as channel mobility and drive current. It was demonstrated that modifying the conventional Si CMOS fabrication process to accommodate the intrinsically meta-stable eSi:C material property is crucial in keeping carbon in its substitutional site thus to preserve strain in the eSi:C stressor throughout the device fabrication process. Significant channel mobility and drive current enhancement was demonstrated in the thick-oxide long-channel nMOS devices using in situ phosphorus-doped (ISPD) epitaxial eSi:C source/drain material.

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Section: In Situ Phosphorus-doped Esi:cmentioning

confidence: 95%

Section: Introductionmentioning

confidence: 99%

Recent Progress and Challenges in Enabling Embedded Si:C Technology

Yang¹,

Ren²,

Takalkar³

et al. 2008

ECS Trans.

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“…[45] Clustered carbon implantation has been proposed as an alternative source of carbon that can achieve higher throughput due to removal of the requirement of pre-amorphization implantation. [46,47,48] Although RTP annealing after C implantation is not desired in order to achieve high strain, it was reported that C implantation and deep N + S/D implantation in sequence, with subsequent RTP and LSA annealing, show improved device performance over N + S/D implantation + RTP annealing followed by C implant + LSA. [49] The carbon implantation depth is recommended to be deeper than that of the N + S/D implant in order to reduce parasitic resistance.…”

Section: Sic Nmos S/d Epimentioning

confidence: 99%

Review paper: Advanced source and drain technologies for low power CMOS at 22/20 nm node and below

Song

Blatchford

2011

Electron. Mater. Lett.

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TX 75243, U.S.A As device dimensions scale, optimization of the source and drain portions of MOSFETs becomes more important in order to reduce parasitic resistance and capacitance, and thus ultimately improve overall device performance. Reduction of parasitic resistance requires careful optimization of dopant incorporation and activation. In current cutting-edge technologies, the source/drain region also plays a key role in improving channel carrier mobility though process-induced strain. Introducing various alloys into NiSi and/or implanting appropriate elements has shown to give significant reduction of the Schottky barrier height between NiSi and Si, thereby improving resistance. In this paper, we review key aforementioned source and drain engineering technologies relevant to the 22/20 nm logic technology node and below.

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“…SiC was experimentally proven and introduced as a source and drain material creating a heterojunction, which induced horizontal tensile strain and vertical compressive strain in the silicon channel, thus increasing the current drive by 50 % for a gate length of 50 nm [3]. An increase in the current drive was depicted in a 40 nm device using SiC as a source/drain material [4]. Z. Ren [5] in 2008 discussed SiC with phosphorus material doping to increase the current.…”

Section: Introductionmentioning

confidence: 99%