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For the first time, embedded Si:C (eSi:C) was demonstrated to be a superior nMOSFET stressor compared to SMT or tensile liner (TL) stressors. eSi:C nMOSFET showed higher channel mobility and drive current over our best poly-gate 45nm-node nMOSFET with SMT and tensile liner stressors. In addition, eSi:C showed better scalability than SMT plus tensile liner stressors from 380nm to 190nm poly-pitches.

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A high performance embedded DRAM with deep trench capacitor and high performance SOI logic has been deployed in 45nm and 32nm technology nodes. Following a yield ramp of the sub-2ns latency 45nm technology, we present, for the first time, a 32nm eDRAM technology fully compatible with high performance logic with high-κ metal gate access transistor and high-κ node dielectric for the deep trench storage capacitor.We also describe the technology advancements required to scale the deep trench as well as the access transistor for optimal cell retention and performance. A clear scaling path is seen for the 22nm technology node.

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