On choosing test criteria for behavioral level hardware design verification

Mayhauser, A. von; Chen, T.; Kok, Jonathan; Anderson, Charles W.; Read, Aaron; Haijar, A.

doi:10.1109/hldvt.2000.889572

Cited by 16 publications

(6 citation statements)

References 22 publications

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“…For the graph illustrated in Fig. 4, possible paths are: a) 1, 2, 3, 4; b) 1,5,6,7,8,9,12,13,14; c) 1,5,6,7,8,10,11,12,13,14; d) 1,5,6,15,16,17,20,21,22; e) 1,5,6,15,16,18,19,20,21,22; f) 1, 5, 6, 15, 23.…”

Section: B Test Vectors Generationmentioning

confidence: 98%

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Improving ATPG Gate-Level Fault Coverage by using Test Vectors generated from Behavioral HDL Descriptions

Krug

Lubaszewski

Moraes³

2006

2006 IFIP International Conference on Very Large Scale Integration

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Current hardware design flows include test pattern generation as a single step to be performed only after logical synthesis. However, early generation of few high level test patterns can provide higher test quality and reduce ATPG effort. In this work, we apply a software engineering technique for control flow based path testing, to extract test vectors from the behavioral HDL description of digital circuits. We show how one can adapt this software testing approach to test hardware devices. Experimental results show that combining high level generated test vectors with gate level ATPG can improve test quality, either increasing fault coverage and/or reducing test set size.

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Section: B Test Vectors Generationmentioning

confidence: 98%

“…Branch coverage criterion was used for design verification of VHDL descriptions in [6]. The original methodology was adapted to cope with the needs imposed by the VHDL language.…”

Section: Previous Workmentioning

confidence: 99%

Improving ATPG Gate-Level Fault Coverage by using Test Vectors generated from Behavioral HDL Descriptions

Krug

Lubaszewski

Moraes³

2006

2006 IFIP International Conference on Very Large Scale Integration

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“…By applying software testing techniques, Mayrhauser et al [32] improve the quality of behavioral models under test. In fact, they propose criteria for the verification of behavioral designs for hardware written in VHDL.…”

Section: Related Workmentioning

confidence: 99%

Enhancing IP cores specifications using hierarchical composition and set theory

Rodrigues

Silva

Cunha

et al. 2011

Des Autom Embed Syst

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During the functional verification, complex interactions between multiple blocks that compose an Intellectual Property (IP) core can reveal hard-to-find bugs. Functional verification specifications must be precise to assure these interactions occur during the simulation. In this work, we are proposing a technique for improving the functional verification specification of individual blocks, preserving the occurrence of these interaction scenarios in the composition phase. Our approach was implemented for the VeriSC methodology, a SystemC-based functional verification methodology. After each block that composes the IP core was stand-alone verified, we exploit the composition phase using set theory to inThis work was partially funded by the Brazil IP project. 226 C.L. Rodrigues et al.crease the coverage numbers and to justify why some of these numbers cannot, or need not, reach 100%. By applying our approach in a MPEG 4 video decoder design, we show how our work can save functional verification time during the hierarchical composition. Using mutation based-tests, we demonstrate that our work can contribute to error detection. Furthermore, we demonstrate the effectiveness of our approach with regard to traditional structural coverage metrics, such as line coverage and branch coverage.

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“…The branch coverage metric has been used for behavioral validation by several researchers for coverage evaluation and test generation [6,7].…”

Section: Control-dataflow Fault Modelsmentioning

confidence: 99%

Fault models and test generation for hardware-software covalidation

Harris

2003

IEEE Des. Test. Comput.

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The increasing use of hardware-software systems in cost-critical and life-critical applications has led to heightened significance of design correctness of these systems. This article presents a summary of research in test generation and fault models to support hardware-software covalidation. The covalidation problem involves the verification of design correctness using simulation-based techniques. The article focuses on the test generation process for hardware-software systems and the fault models which support test generation.

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On choosing test criteria for behavioral level hardware design verification

Cited by 16 publications

References 22 publications

Improving ATPG Gate-Level Fault Coverage by using Test Vectors generated from Behavioral HDL Descriptions

Improving ATPG Gate-Level Fault Coverage by using Test Vectors generated from Behavioral HDL Descriptions

Enhancing IP cores specifications using hierarchical composition and set theory

Fault models and test generation for hardware-software covalidation

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