Improving ATPG Gate-Level Fault Coverage by using Test Vectors generated from Behavioral HDL Descriptions

Abstract

Current hardware design flows include test pattern generation as a single step to be performed only after logical synthesis. However, early generation of few high level test patterns can provide higher test quality and reduce ATPG effort. In this work, we apply a software engineering technique for control flow based path testing, to extract test vectors from the behavioral HDL description of digital circuits. We show how one can adapt this software testing approach to test hardware devices. Experimental results show that combining high level generated test vectors with gate level ATPG can improve test quality, either increasing fault coverage and/or reducing test set size.

Fast Multi-level Test Generation at the RTL

“…In future executions of the path this amount is adjusted based on the percentage of uncovered points for Algorithm 2 Ant Search with Targeted Input Generation 1: S branch = uncovered blocks() 2: for all ants k = 1 to K do 3: for all cycles c = 1 to N c do 4: generate input() 5: evalutate path() 6: while n gen < TIMEOUT do 7: regenerate input() 8: evaluate path() 9: if path pheromones > threshold then 10 …”

“…However, all these methods utilize macro level code coverage metrics, such as branch coverage, which do not adequately represent lower level behavior within the design. To combat this, mixed level generation is used in [10][11][12], these methods generate vectors at the RTL and then refine the generation process using information from gate level simulation or test generation. However, the invocation of gate-level fault simulation significantly slows these methods and the full benefit of generation at the RTL is not realized.…”