Prototyping Generators for on-line test vector generation based on PSL properties

Oddos, Y.; Morin-Allory, Katell; Borrione, D.

doi:10.1109/ddecs.2007.4295317

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Cited by 4 publications

(2 citation statements)

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“…Assertions have been found to be beneficial for solving a wide range of tasks in systems design ranging from modeling, verification and even manufacturing test [1]. In this paper we consider assertion-based verification which has been recognized as an efficient approach to cope with many difficulties in the state-of-the-art digital systems functional verification.…”

Section: Introductionmentioning

confidence: 99%

Temporally Extended High-Level Decision Diagrams for PSL Assertions Simulation

Jenihhin

Raik

Chepurov

et al. 2008

2008 13th European Test Symposium

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Section: Introductionmentioning

confidence: 99%

Temporally Extended High-Level Decision Diagrams for PSL Assertions Simulation

Jenihhin

Raik

Chepurov

et al. 2008

2008 13th European Test Symposium

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“…A number of approaches aiming hardware checkers creation from assertions meant for prototype verification/validation by emulation (a development flow phase standing before mass-production), such as [2], [10], [11], [12], [13] can be extended for this purpose. The most widely known commercial tool for usual assertions conversion to their synthesizable form is FoCs from IBM [16], [17].…”

Section: Introductionmentioning

confidence: 99%

On reusability of verification assertions for testing

Jenihhin

Raik

Ubar

et al. 2008

2008 11th International Biennial Baltic Electronics Conference

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Assertions have proven to be an effective mechanism to improve quality and to speed-up simulationbased design verification. They are created and embedded to the simulatable design description by the designer, the person with the deepest knowledge about the desired functionality and its real implementation. In this paper we propose to reuse this valuable information during the design manufacturing testing phase to increase the test quality and efficiency. The paper considers different types of design properties created for verification such as environmental assumptions and internal signal assertions. The reusable information is proposed to be applied for test pattern generation, embedded test observability improvement and DfT (design for testability) enhancement.

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