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A b s t r a c tThe widespread use of field programmable gate arrays (FPGAs) as components in highperformance systems has increased the significance of path delay faults in FPGAs. We present a technique for FPGA path delay fault detection which integrates test insertion with the FPGA placement and routing stages to accomplish testing with low test application time. An accurate static timing analyzer is used to identify critical paths and built-in selftest (BIST) hardware is inserted using a placement and routing tool. Initial experimental results show that testing is accomplished with low test application time for several benchmark designs.

The increasing use of hardware-software systems in cost-critical and life-critical applications has led to heightened significance of design correctness of these systems. This article presents a summary of research in test generation and fault models to support hardware-software covalidation. The covalidation problem involves the verification of design correctness using simulation-based techniques. The article focuses on the test generation process for hardware-software systems and the fault models which support test generation.

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The testability of a VLSI design is strongly aected by its register-transfer level (RTL) structure. Since the high-level synthesis process determines the RTL structure, it is necessary to consider testability during high-level synthesis. A synthesis system composed of scheduling and binding components minimizes the number of hardware sharing conicts between tests in the test schedule. Novel test conict estimates are used to direct the synthesis process. The test conict estimation is based on examination of the interconnect structure of the partial design state during synthesis. Test conict estimates enable our synthesis system to select design options which increase test concurrency, thereby decreasing test time. Experimental results show that designs generated by this approach are testable in a highly concurrent manner. INTRODUCTIONThe cost of chip testing has become a large fraction of the total chip production expenditure as other cost components have improved. Furthermore, increasing gate-to-pin ratios limit the feasibility of testing chips externally. The incorporation of test structures into the design ameliorates the testability of hardware which is not easily testable through external pins. The Built-In Self-Test BIST approach ([2], [11]) tests chip components using pseudo-random patterns which are generated onchip. Consequently, testing can be performed on-site with minimal additional testing equipment, and at chip speed. BIST requires the placement of pseudo-random pattern generators (PRPG) and multiple-input signature registers (MISR) on the chip. PRPGs generate pseudo-random patterns to test the combinational modules on the chip and MISRs compact the results of the tests. All test registers are in a shift register chain so that seeds to the PRPGs can be shifted in at the beginning of testing, and compacted results can be shifted out of the MISRs after testing.High chip test time reduces chip production throughput and increases chip production cost. In order to minimize test time, as many tests as possible should be executed in parallel, yet total parallelization is often impossible due to hardware sharing conicts between tests. Hardware sharing conicts occur because the test results of two dierent hardware modules may be forced to propagate through the same hardware in order to arrive at a MISR. Such conicts occur as a result of the nature of the interconnect structure between dierent modules in the datapath. Considering test concurrency during high-level synthesis may greatly improve test time since the structural representation is determined at that stage.Previous research concentrates on the eect of self-loops and sequential depth from test registers. Such approaches may increase the testability of a design, but they only indirectly address the problem of conicts between tests. It is the test conicts which increase test time by requiring that tests be executed sequentially. Since reduction of self-loops and sequential depth only resolves part of the test conict problem, those approaches may degrad...

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