BIST-based delay path testing in FPGA architectures

Abstract

A b s t r a c tThe widespread use of field programmable gate arrays (FPGAs) as components in highperformance systems has increased the significance of path delay faults in FPGAs. We present a technique for FPGA path delay fault detection which integrates test insertion with the FPGA placement and routing stages to accomplish testing with low test application time. An accurate static timing analyzer is used to identify critical paths and built-in selftest (BIST) hardware is inserted using a placement and routing tool. Initial experimental results show that testing is accomplished with low test application time for several benchmark designs.

BIST of delay faults in the logic architecture of symmetrical FPGAs

“…Techniques have been proposed to test either the whole FPGA structure before it is shipped to the user in a Manufacturing-Oriented Test (MOT) context [1,2,5,10,12,15,16,17,18,19,20] or only the used parts of the FPGA programmed for a user application in an Application-Oriented Test (AOT) context [11,13,14,16]. The first proposed techniques can be used for static voltage testing [1,10,12,15,16,17,18,19] and consider faults in the logic cells [1,12,16,17,18], in the routing architecture [1,10,17,19], or in the configuration layer [16,17].…”

“…The first proposed techniques can be used for static voltage testing [1,10,12,15,16,17,18,19] and consider faults in the logic cells [1,12,16,17,18], in the routing architecture [1,10,17,19], or in the configuration layer [16,17]. Some of these techniques use a BIST architecture by configuring unused parts of the FPGA [2,11,18,19].…”

“…Unfortunately, testing delay faults in FPGAs is still an immature field and only few approaches have been proposed [2,5,11,13,14,20]. In the remaining paragraph, we try to summarize the main points of recent published works.…”

“…In the remaining paragraph, we try to summarize the main points of recent published works. In [11,13,14], the objective is to detect delay faults in an AOT context. The approach developed in [13,14] proposes to test each (critical) path of the design after customisation of the logic cells belonging to the tested path.…”

“…This is done to allow transition propagations on the tested path whatever the values on the side inputs and to preserve the possibilities of the inputoutput transition polarity of the original function. In [11], this process is applied in a BIST environment where a simple counter is used to control the LUT inputs and to generate the required transitions. In [2,5,20], the main objective is to detect delay faults in a MOT context.…”