On-chip ramp generators for mixed-signal BIST and ADC self-test

Provost, B.; Sánchez-Sinencio, E.

doi:10.1109/jssc.2002.807415

Cited by 124 publications

(53 citation statements)

References 19 publications

(21 reference statements)

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“…If we express k = tq + s, then the index k will span the linear space from 0 to N when t and s span the linear space from 0 to p − 1 and 1 to q, respectively, where we are again assuming that pq = N . It follows from (6) and (14) …”

Section: Mathematical Assessment Of Ddem Testing Performancementioning

confidence: 95%

A Deterministic Dynamic Element Matching Approach for Testing High-Resolution ADCs With Low-Accuracy Excitations

Olleta

Jiang

Chen

et al. 2006

IEEE Trans. Instrum. Meas.

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Abstract-Dynamic element matching (DEM) is capable of providing good average linearity performance in matching critical circuits in the presence of major component mismatch, but the approach has received minimal industrial adoption outside of Σ−∆ structures because of challenges associated with implementation of a required randomizer and because of the time-local nonstationarity. This paper presents a DEM approach to analog-to-digital converter (ADC) testing in which low-precision DEM digitalto-analog converters (DACs) are used to generate stimulus signals for ADCs under test. It is shown that in a testing environment, this approach provides very high precision test results, and timelocal nonstationarity is of no concern. In addition to traditional random DEM techniques, a deterministic DEM (DDEM) strategy that eliminates the need for a randomizer is introduced. The performance of the DDEM method is established mathematically and validated with detailed simulation results. Furthermore, the DDEM method requires far fewer samples to achieve the same level of average linearity than the random DEM approach. It is demonstrated that both the random DEM and DDEM methods can be used to accurately test ADCs with linearity that far exceeds that of the DAC used as a signal generator. This technique of using imprecise excitations and DEM to test much more accurate ADCs offers potential for use in both production test and built-in self-test environments where high linearity test sources are difficult to implement.Index Terms-Analog-to-digital converter (ADC) testing, built-in self-test (BIST), dynamic element matching (DEM), integral nonlinearity (INL) testing.

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Section: Mathematical Assessment Of Ddem Testing Performancementioning

confidence: 95%

A Deterministic Dynamic Element Matching Approach for Testing High-Resolution ADCs With Low-Accuracy Excitations

Olleta

Jiang

Chen

et al. 2006

IEEE Trans. Instrum. Meas.

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“…For functionality evaluation, a ramp signal is applied to the ADC. A full scale ramp input signal is an ideal waveform for testing an ADC since it causes generation of all the possible codes (having 64 codes for a six-bit ADC) [35][36][37][38][39][40]. Regarding the applied ramp signal, its maximum amplitude is 0.3 V, slope starting point is at 5 µs, and slope ending point is at 87 µs.…”

Section: Resultsmentioning

confidence: 99%

Security Interrogation and Defense for SAR Analog to Digital Converter

2017

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Nowadays, the analog and mixed-signal intellectual property (IP) cores play an important role in system on chip (SoC) design due to their capabilities in performing critical functions. These IPs can be the target of adversaries similar to their digital counterparts. In this work, we study the security aspects of a tunnel field effect transistor (TFET)-based six-bit successive approximation register (SAR) analog to digital converter (ADC) through proposing two threats and two countermeasures that target the output signals of the ADC datapath and its control unit. The datapath-based threat manipulates the exiting signals from the register file, and its countermeasure attempts to filter the ADC output based on the convention of having ±1 least significant bit variation (at maximum) between the adjacent sampled data points. The control-based threat manipulates the exiting signals from the control unit, and its countermeasure is a trustworthy replication of a part of the ADC circuit that is used to provide reference data for security examination and output filtering.

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“…Translating these constraints into accuracy figures, both mean at least two more resolution bits than that of the ADC to be tested. Some authors have been dealing either with the implementation of high resolution signals for on-chip testing [1][2][3][4] or with devising simpler measurement procedures [5].…”

Section: A Relaxing Input Requirementsmentioning

confidence: 99%