Offset correction system for 128-channel self-triggering readout chip with in-channel 5-bit energy measurement functionality

Otfinowski, Piotr; Gryboś, P.; Szczygieł, R.; Kasiński, Krzysztof

doi:10.1016/j.nima.2015.01.048

Cited by 8 publications

(2 citation statements)

References 11 publications

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“…STS-XYTER2 is a 10 mm × 6.8 mm sized prototype STS readout ASIC fabricated in 2016 in UMC 180 nm CMOS process. Its analog front-end (AFE), containing a charge-sensitive amplifier, a two-path shaper stage, a 5-bit continuous-time ADC [7] and a timing discriminator, is optimized for specific conditions of the STS detector [5,6] including co-design of the sensor, cable, ASIC and power supply. The ASIC is self-contained and requires very little external components.…”

Section: Jinst 12 C03023mentioning

confidence: 99%

System-level considerations for the front-end readout ASIC in the CBM experiment from the power supply perspective

et al. 2017

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A: New fixed target experiments using high intensity beams with energy up to 10 AGeV from the SIS100 synchrotron presently being constructed at FAIR/GSI are under preparation. Most of the readout electronics and power supplies are expected to be exposed to a very high flux of nuclear reaction products and have to be radiation tolerant up to 3 MRad (TID) and sustain up to 10 14 /cm 2 of 1 MeV neutron equivalent in their life time. Moreover, the mostly minimum ionising particles under investigation leave very little signal in the sensors. Therefore very low noise level amplitude measurements are required by the front-end electronics for effective tracking. Sensor and interconnecting micro-cable capacitance and series resistance in conjunction with intrinsic noise of the charge sensitive amplifier are dominant noise sources in the system. However, the singleended architecture of the amplifiers employed for the charge processing channels implies a potential problem with noise contributions from power supply sources. Strict system-level constraints leave very little freedom in selecting a power supply structure optimal with respect to: power efficiency, cooling capabilities and power density on modules, but also noise injection to the front-end via the power supply lines. Design of the power supply and distribution system of the Silicon Tracking System in the CBM experiment together with details on the front-end ASICs (STS -XYTER2) and measurement results of power supply and conditioning electronics (selected DC/DC converter and LDO regulators) are presented. K: Voltage distributions; Front-end electronics for detector readout; Radiation-hard electronics 1Corresponding author.

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Section: Jinst 12 C03023mentioning

confidence: 99%

System-level considerations for the front-end readout ASIC in the CBM experiment from the power supply perspective

et al. 2017

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“…First, the rising edge of the fast path triggers the timestamp latch via latch_ts signal. As soon as the slower path signal triggers the lowest threshold discriminator in a continuous-time flash ADC [12], the latched timestamp value is blocked. The ADC output reflects the amplitude of the pulse but the conversion cycle is over when the signal almost returns to the baseline (lowest threshold discriminator in the ADC is off).…”

Section: Front-end To Back-end Interfacementioning

confidence: 99%

Back-end and interface implementation of the STS-XYTER2 prototype ASIC for the CBM experiment

2016

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Each front-end readout ASIC for the High-Energy Physics experiments requires robust and effective hit data streaming and control mechanism. A new STS-XYTER2 full-size prototype chip for the Silicon Tracking System and Muon Chamber detectors in the Compressed Baryonic Matter experiment at Facility for Antiproton and Ion Research (FAIR, Germany) is a 128-channel time and amplitude measuring solution for silicon microstrip and gas detectors. It operates at 250 kHit/s/channel hit rate, each hit producing 27 bits of information (5-bit amplitude, 14-bit timestamp, position and diagnostics data). The chip back-end implements fast front-end channel read-out, timestamp-wise hit sorting, and data streaming via a scalable interface implementing the dedicated protocol (STS-HCTSP) for chip control and hit transfer with data bandwidth from 9.7 MHit/s up to 47 MHit/s. It also includes multiple options for link diagnostics, failure detection, and throttling features. The back-end is designed to operate with the data acquisition architecture based on the CERN GBTx transceivers. This paper presents the details of the back-end and interface design and its implementation in the UMC 180 nm CMOS process.

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Low area 4-bit 5 MS/s flash-type digitizer for hybrid-pixel detectors – Design study in 180 nm and 40 nm CMOS

Otfinowski

Gryboś

2015

Nuclear Instruments and Methods in Physics Research Section A:

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Offset correction system for 128-channel self-triggering readout chip with in-channel 5-bit energy measurement functionality

Cited by 8 publications

References 11 publications

System-level considerations for the front-end readout ASIC in the CBM experiment from the power supply perspective

System-level considerations for the front-end readout ASIC in the CBM experiment from the power supply perspective

Back-end and interface implementation of the STS-XYTER2 prototype ASIC for the CBM experiment

Low area 4-bit 5 MS/s flash-type digitizer for hybrid-pixel detectors – Design study in 180 nm and 40 nm CMOS

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