Observation of one-fifth-of-a-clock wake-up time of power-gated circuit

Miyazaki, Taeko; Canh, Tran Quang; Kawaguchi, Hiroshi; Sakurai, Takayasu

doi:10.1109/cicc.2004.1358743

Cited by 16 publications

(6 citation statements)

References 10 publications

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“…Input forcing circuit [6,7] is a circuit that is located at each primary input to provide the corresponding bit value of the sleep vector (see Figure 1). The one that provides logic high, a block labeled input forcing one in Figure 2, is placed in FCR and the one that provides logic low, a block labeled input forcing zero in Figure 2, is placed in HCR due to the availability of V dd and V ss , respectively.…”

Section: Cell-based Design Of Zpg Cir-cuitsmentioning

confidence: 99%

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Multiobjective optimization of sleep vector for zigzag power-gated circuits in standard cell elements

Paik

Shin

2008

Proceedings of the 45th Annual Design Automation Conference

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Zigzag power gating (ZPG) has been proposed to alleviate the drawback of power gating in its long wake-up delay, thereby broadening the application of power gating to suppressing active-as well as standby-leakage. However, complicated power network due to the use of nMOS and pMOS switches in zigzag fashion has limited its application to custom circuits. Heterogeneous use of power rails inevitably incurs overhead of area and wirelength during physical design. Furthermore, the use of sleep vector causes additional switching power when entering standby mode and returning back to active mode. The switching power should be minimized not to outweigh the leakage saving by employing ZPG scheme. In this paper, we propose a complete power network architecture, which allows us to use unmodified standard cell elements for implementing ZPG circuits. We formulate selecting sleep vector as a multiobjective optimization problem, minimizing transition energy and total wirelength. We solve the problem by employing multiobjective genetic-based algorithm. Experimental results show the saving of 39% in transition energy and 8% in wirelength, on average, for several benchmark circuits in 65-nm technology. The complete design flow starting from RTL description down to layout is proposed, and assessed with 65-nm technology.

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Section: Cell-based Design Of Zpg Cir-cuitsmentioning

confidence: 99%

“…But, the wake-up delay is still too large [2,3] or the amount of leakage saving is not large enough [4]. Zigzag power gating (ZPG) [5][6][7] has been shown to achieve the best balance of leakage saving and wake-up delay. Figure 1 shows the concept of ZPG circuit.…”

Section: Introductionmentioning

confidence: 99%

Multiobjective optimization of sleep vector for zigzag power-gated circuits in standard cell elements

Paik

Shin

2008

Proceedings of the 45th Annual Design Automation Conference

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“…Zigzag power-gating scheme [6][7] can reduce the wake-up time to less than 1/5 of a clock cycle. Thus zigzag CMOS can be used as a substitute technique for clock gating when the clock gating loses its merit in a leakage-dominant era.…”

Section: Introductionmentioning

confidence: 99%

95% Leakage-Reduced FPGA using Zigzag Power-gating, Dual-VTH/VDD and Micro-VDD-Hopping

Tran

Kawaguchi

Sakurai

2005

2005 IEEE Asian Solid-State Circuits Conference

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Low-power FPGA architecture is proposed based on fine-grained V DD control scheme called micro-V DD -hopping. Four Configurable Logic Blocks (CLB) are grouped into one block where V DD is shared. In the micro-V DD -hopping scheme, V DD of each block is varied between the higher V DD (V DDH ) and the lower V DD (V DDL ) spatially and temporally to achieve lower power, while keeping performance undegraded. A level shifter that has less contention is proposed. The FPGA also incorporates Zigzag power-gating scheme, special care has been taken to cope with sneak leakage path problem. The proposed FPGA is fabricated using 0.35µm CMOS technology together with the conventional fixed-V DD FPGA. Measurement shows that the dynamic power can be reduced by 86% when the required speed is half of the highest speed.Simulation using 90nm CMOS technology shows that a leakage power reduction of 95% can be achieved, when the proposed method is used. Area overhead of the proposed FPGA is 2%.

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“…They also proposed an approach to put the execution units into sleep when a branch misprediction is detected. Tschanz, et al [4] and Miyazaki, et al [5] discussed circuit-level techniques to dynamically control the power switches for adders with fast time constants for entering and exiting the idle mode. In contrast, in paper [6] the authors proposed logic-level RTPG for finite state machine (FSM) circuits.…”

Section: Introductionmentioning

confidence: 99%

A Design Approach for Fine-grained Run-Time Power Gating using Locally Extracted Sleep Signals

Usami

Ohkubo

2006

2006 International Conference on Computer Design

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Abstract-Leakage power dissipation becomes a dominant component in operation power in nanometer devices. This paper describes a design methodology to implement runtime power gating in a fine-grained manner. We propose an approach to use sleep signals that are not off-chip but are extracted locally within the design. By utilizing enable signals in a gated clock design, we automatically partition the design into domains. We then choose the domains that will achieve the gain in energy savings by considering dynamic energy overhead due to turning on/off power switches. To help this decision we derive analytical formulas that estimate the break-even point. For the domains chosen, we create power gating structure by adding power switches and generating control logic to the switches. We experimentally built a design flow and evaluated with a synthesizable RTL code for a microprocessor and a 90nm CMOS device model both used in industry. Results from applying to a datapath showed that the break-even point that achieves the gain exists in the number of enables controlling the power switch. By applying the domains controlled by up to 3 enables achieved the active leakage savings by 83% at the area penalty by 20%.

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Observation of one-fifth-of-a-clock wake-up time of power-gated circuit

Cited by 16 publications

References 10 publications

Multiobjective optimization of sleep vector for zigzag power-gated circuits in standard cell elements

Multiobjective optimization of sleep vector for zigzag power-gated circuits in standard cell elements

95% Leakage-Reduced FPGA using Zigzag Power-gating, Dual-VTH/VDD and Micro-VDD-Hopping

A Design Approach for Fine-grained Run-Time Power Gating using Locally Extracted Sleep Signals

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