Novel single-poly EEPROM with damascene control-gate structure

Sung, Hung-Cheng; Lei, Tan Fu; Hsu, Te-Hsun; Wang, S.W.; Kao, Ya-Chen; Lin, Yung-Tao; Wang, C.S.

doi:10.1109/led.2005.856014

Cited by 9 publications

(4 citation statements)

References 7 publications

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“…In recent efforts, a stacked metal-insulator-metal (MIM) and an n-well capacitor have been applied to a single polysilicon EEPROM cell in order to increase memory capacity [1][2][3][4]. The application of the single polysilicon EEPROM is becoming more popular due to its low process cost and satisfactory reliability [5][6][7]. Optimal characteristics of EEPROM include fast program/erase speed, high endurance performance, and low leakage current.…”

Section: Introductionmentioning

confidence: 99%

Effect of MIM and n-Well Capacitors on Programming Characteristics of EEPROM

Lee¹,

Cui²,

Jin³

et al. 2011

Transactions on Electrical and Electronic Materials

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An electrically erasable programmable read-only memory (EEPROM) containing a stacked metal-insulator-metal (MIM) and n-well capacitor is proposed. It was fabricated using a 0.18 μm standard complementary metal-oxide semiconductor process. The depletion capacitance of the n-well region was effectively applied without sacrificing the cell-area and control gate coupling ratio. The device performed very similarly to the MIM capacitor cell regardless of the smaller cell area. This is attributed to the high control gate coupling ratio and capacitance. The erase speed of the proposed EEPROM was faster than that of the cell containing the MIM control gate.

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Section: Introductionmentioning

confidence: 99%

Effect of MIM and n-Well Capacitors on Programming Characteristics of EEPROM

Lee¹,

Cui²,

Jin³

et al. 2011

Transactions on Electrical and Electronic Materials

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“…Nowadays, a single-poly electrically erasable programmable read-only memory (EEPROM) is one of the promising solutions for low-cost embedded nonvolatile memory (NVM) applications [1][2][3][4][5][6][7]. A diffused N-well is used as a control gate (CG) in the conventional single-poly EEPROM [1][2][3], which may lead to some problems, such as the large junction capacitance and resistance at the CG, the reduction of the coupling factor (α CG ) and the disturbance to adjacent blocks during CG operation through the substrate [4].…”

Section: Introductionmentioning

confidence: 99%

“…A diffused N-well is used as a control gate (CG) in the conventional single-poly EEPROM [1][2][3], which may lead to some problems, such as the large junction capacitance and resistance at the CG, the reduction of the coupling factor (α CG ) and the disturbance to adjacent blocks during CG operation through the substrate [4]. Recently, metallic CG EEPROM cells with a damascene CG, metalinsulator-metal (MIM) capacitor and polysilicon fingershape (polyfinger) capacitor have been reported as possible solutions to these problems and attracted much attention [4][5][6]. However, these approaches require additional process steps [4,5] or a large cell area and high operation voltage due to small α CG [6].…”

Section: Introductionmentioning

confidence: 99%

“…Recently, metallic CG EEPROM cells with a damascene CG, metalinsulator-metal (MIM) capacitor and polysilicon fingershape (polyfinger) capacitor have been reported as possible solutions to these problems and attracted much attention [4][5][6]. However, these approaches require additional process steps [4,5] or a large cell area and high operation voltage due to small α CG [6].…”

Section: Introductionmentioning

confidence: 99%

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Performance improvement of the EEPROM cells with the standard logic process featuring a metal finger coupling capacitor

Tang¹,

Huang²,

Wu³

et al. 2010

Semicond. Sci. Technol.

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In this paper, a novel single-poly electrically erasable programmable read-only memory (EEPROM) using a metal finger coupling capacitor is proposed and fabricated with a pure logic CMOS process. The metal interconnect layer is applied to form the finger-type capacitor which can be used as the coupling capacitor in the EEPROM cell. Using the metal finger capacitor, the proposed cell exhibits the advantages of a metallic control gate and features a higher coupling ratio to achieve smaller cell area and lower program/erase voltage. The program/erase characteristics, endurance and retention performances are presented. In addition, the EEPROM cell with a stacked metal finger structure can further improve the coupling ratio. Thus, lower operation voltage can be obtained without increasing the cell area.

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