Novel Low-Complexity and Low-Power Flip-Flop Design

Lin, Jin-Fa; Hong, Zheng-Jie; Tsai, Chang-Ming; Wu, Bo-Cheng; Yu, Shao-Wei

doi:10.3390/electronics9050783

Cited by 8 publications

(4 citation statements)

References 19 publications

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“…For this application various kinds of sense amplifiers has been utilized for sensing ultra-low voltage present at bit lines and amplify them with the help of pair of transistors in a positive feedback manner to improve the performance of whole memory subsystem. Most of the previous work on SAFF has been reported using CMOS technology [16][17][18][19][20]. There is no previous available literature on CNTFET based SAFF designs.…”

Section: Investigation Of Sense Amplifier Based Single Edge Trigger D...mentioning

confidence: 99%

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Implementation and Optimization of CNTFET Based Ultra-Low Energy Delay Flip Flop Designs

Swami

Sharma²

2022

Silicon

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Energy conservation and delay minimization are the two major goals while designing ultra-low-power digital integrated circuits at lower technology nodes. Here, silicon based carbon nanotube field effect transistor (CNTFET) has been explored as a novel material for future electronics design applications (EDA). In this paper, two energy-efficient switching activity minimization techniques have been applied with proposed designs. First technique detects the completion of sensing stage operation known as transition completion detection (TCD) technique. TC signal generated from NAND operation of complementary outputs of sensing stage which minimizes glitches in the complementary outputs of the latch stage. Another clock gating mechanism applied at the latch stage to smoothen the output waveforms Q and Q. The proposed and existing designs simulated using 32nm CMOS and 32nm CNT-FET technology, indicating that the CNTFET based design reduces power by 45% and 36% respectively in comparison with conventional CMOS. Proposed Low Power Sense Amplifier Flip Flop with transition control detection (TCD-LPSAFF) and Ultra Low Energy Sense Amplifier Flip Flop (ULESAFF) give minimal power delay product (PDP) which is 35.7 × 10 −18 J and 29.6 × 10 −18 J respectively. Also, the effect of process variation has been analyzed at specified corners (FF, TT and SS) in the temperature range of -40 • C to 120 • C. The performance of all designs has been validated by functionality testing with variation in load cpacitance, diameter, number of tubes and pitch respectively.

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Section: Investigation Of Sense Amplifier Based Single Edge Trigger D...mentioning

confidence: 99%

“…Still, LPSAFF required a lot of improvement at slow working NAND based D latch circuitry. A variety of slave latch structures for low power SAFF are explored [15][16][17][18][19][20][21][22][23][24][25]. A modified latch design introduced by Nikolic is explained in [21].…”

Section: Low Power Sense Amplifier Flip Flop (Lpsaff)mentioning

confidence: 99%

Implementation and Optimization of CNTFET Based Ultra-Low Energy Delay Flip Flop Designs

Swami

Sharma²

2022

Silicon

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“…Very-large-scale integration (VLSI) designers are continuously trying to mitigate the large power dissipation in the nanoscale region by applying various techniques so that leakage power does not hinder the growth of the electronics industry. There are several ways to minimize leakage power in VLSI designs [3,4]. Different abstraction levels such as system, architecture, device, algorithm, and transistor levels are used for leakage reduction.…”

Section: Introductionmentioning

confidence: 99%

A novel approach for designing of variability aware low‐power logic gates

Sharma

2022

ETRI Journal

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Metal‐oxide‐semiconductor field‐effect transistors (MOSFETs) are continuously scaling down in the nanoscale region to improve the functionality of integrated circuits. The scaling down of MOSFET devices causes short‐channel effects in the nanoscale region. In nanoscale region, leakage current components are increasing, resulting in substantial power dissipation. Very large‐scale integration designers are constantly exploring different effective methods of mitigating the power dissipation. In this study, a transistor‐level input‐controlled stacking (ICS) approach is proposed for minimizing significant power dissipation. A low‐power ICS approach is extensively discussed to verify its importance in low‐power applications. Circuit reliability is monitored for process and voltage and temperature variations. The ICS approach is designed and simulated using Cadence's tools and compared with existing low‐power and high‐speed techniques at a 22‐nm technology node. The ICS approach decreases power dissipation by 84.95% at a cost of 5.89 times increase in propagation delay, and improves energy dissipation reliability by 82.54% compared with conventional circuit for a ring oscillator comprising 5‐inverters.

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“…With the development of new process technology, the design method of FF continues to develop. Specific application requirements such as low voltage, low power, low cost or high performance also require new designs [ 6 , 7 , 8 , 9 , 10 , 11 , 12 , 13 , 14 , 15 , 16 , 17 , 18 , 19 , 20 , 21 , 22 , 23 , 24 ]. In this work, the FF design goal is a low voltage and low power consumption with a compact layout area design solution.…”

Section: Introductionmentioning

confidence: 99%

Low-Voltage and Low-Power True-Single-Phase 16-Transistor Flip-Flop Design

Lin

Hong

et al. 2022

Sensors

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A low-voltage and low-power true single-phase flip-flop that minimum the total transistor count by using the pass transistor logic circuit scheme is proposed in this paper. Optimization measures lead to a new flip-flop design with better various performances such as speed, power, energy, and layout area. Based on post-layout simulation results using the TSMC CMOS 180 nm and 90 nm technologies, the proposed design achieves the conventional transmission-gate-based flip-flop design with a 53.6% reduction in power consumption and a 63.2% reduction in energy, with 12.5% input data switching activity. In order to further the performance parameters of the proposed design, a shift-register design has been realized. Experimental measurements at 0.5 V/0.5 MHz show that this proposed design reduces power consumption by 47.3% while achieving a layout area reduction of 30.5% compared to the conventional design.

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Novel Low-Complexity and Low-Power Flip-Flop Design

Cited by 8 publications

References 19 publications

Implementation and Optimization of CNTFET Based Ultra-Low Energy Delay Flip Flop Designs

Implementation and Optimization of CNTFET Based Ultra-Low Energy Delay Flip Flop Designs

A novel approach for designing of variability aware low‐power logic gates

Low-Voltage and Low-Power True-Single-Phase 16-Transistor Flip-Flop Design

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