Novel Gate-All-Around Poly-Si TFTs With Multiple Nanowire Channels

Liao, Ta-Chuan; Tu, Shih-Wei; Yu, Menghan; Lin, Wey Jinq; Liu, Cheng-Chin; Chang, Kang-Ming; Tai, Ya‐Hsiang; Cheng, Huang–Chung

doi:10.1109/led.2008.2001176

Cited by 52 publications

(23 citation statements)

References 20 publications

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“…However, the short channel effect is exacerbated as the channel length decreases. Three-dimensional (3-D) multi-gate structures, such as double-gate, tri-gate, and gate-all-around (GAA) structures, have been proposed to improve gate controllability and protect against the short-channel effects of nanoscale transistors [17][18][19][20][21][22][23][24]. Therefore, a tri-gate fin-like structure with a channel length (L) of 0.2 µm was employed in this study.…”

Section: Introductionmentioning

confidence: 99%

Improving the Gate-Induced Drain Leakage and On-State Current of Fin-Like Thin Film Transistors with a Wide Drain

Zeng

Chen

2018

Applied Sciences

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Polycrystalline silicon (poly-Si) thin film transistors (TFT) with a tri-gate fin-like structure and wide drain were designed and simulated to improve gate-induced drain leakage (GIDL), ON-state current, and breakdown voltage. The GIDL of fin-like TFTs (FinTFTs) examined in this study was dominated by longitudinal band-to-band tunneling (L-BTBT). Extending the wide drain can effectively suppress the longitudinal electric field near the drain and improve L-BTBT GIDL and breakdown. In addition, a wider drain can lead to a large cross section in the current path and improve the ON-state current. FinTFTs with wide drain exhibit a low GIDL, a high ON-state current, and high breakdown voltage, while maintaining favorable gate controllability.

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Section: Introductionmentioning

confidence: 99%

Improving the Gate-Induced Drain Leakage and On-State Current of Fin-Like Thin Film Transistors with a Wide Drain

Zeng

Chen

2018

Applied Sciences

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“…7,21 A spacer acting as a hard mask was used for plasma etching, and a self-aligned nickel silicidation process was used to generate SB interface between SiNW channel and NiSi source/drain electrodes. Strain was induced in SiNW channel by joule heating.…”

Section: Introductionmentioning

confidence: 99%

Enhancement of programming speed on gate-all-around poly-silicon nanowire nonvolatile memory using self-aligned NiSi Schottky barrier source/drain

Chang

Chiou

2013

Journal of Applied Physics

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The programming characteristics of gate-all-around silicon-oxide-nitride-oxide silicon (SONOS) nonvolatile memories are presented using NiSi/poly-Si nanowires (SiNW) Schottky barrier (SB) heterojunctions. The non-uniform thermal stress distribution on SiNW channels due to joule heating affected the carrier transport behavior. Under a high drain voltage, impact ionization was found as a large lateral field enhances carrier velocity. As gate voltage (Vg) increased, the difference in the drain current within a range of various temperature conditions can be mitigated because a high gate field lowers the SB height of a NiSi source/SiNW/NiSi drain junction to ensure efficient hot-carrier generation. By applying the Fowler-Nordheim programming voltage to the SONOS nanowire memory, the SB height (Φn = 0.34 eV) could be reduced by image force; thus, hot electrons could be injected from SB source/drain electrodes into the SiN storage node. To compare both SiNW and Si nanocrystal SONOS devices, the SB SiNW SONOS device was characterized experimentally to propose a wider threshold-voltage window, exhibiting efficient programming characteristics.

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“…Various technologies, including solid-phase crystallization, metalinduced crystallization, excimer laser crystallization (ELC), and continuous-wave laser crystallization (CLC), have been proposed to enlarge grain size for improving the LTPS TFTs [3]- [7]. Among the LTPS technologies, the grain size and quality of polycrystalline silicon (poly-Si) films via CLC process are the largest and the best, hence metaloxide-semiconductor field-effect transistors (MOSFETs) fabricated by CLC opened up the field of silicon-oninsulator (SOI) [9], [10].…”

mentioning

confidence: 99%

“…However, grain boundaries still affect the performance of LTPS TFTs, such as the device uniformity, subthreshold swing (S.S.), on/off ratio, mobility, etc. Therefore, a number of articles reported about the methods of nanowire (NW) channel processing to enhance the performance and uniformity of devices [3]- [5], [7]. On the other hand, for advanced large-scale integration circuits, strained-Si technologies are increasingly important when device size is scaling down.…”

mentioning

confidence: 99%

High-Performance Single-Crystal-Like Strained-Silicon Nanowire Thin-Film Transistors via Continuous-Wave Laser Crystallization

Chou

Chan

Lee

et al. 2015

IEEE Electron Device Lett.

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High-performance polycrystalline-silicon nanowire (NW) thin-film transistors (TFTs) have been demonstrated via continuous-wave laser crystallization (CLC) to exhibit the low subthreshold swing of 216 mV/decade and high ON/OFF ratio of 1.6×10 9 . In addition, the thermal stress of ∼800 MPa induced from the CLC process also contributed to the single-crystal-like silicon NW CLC TFTs to achieve an excellent field-effect mobility of up to 900 cm 2 V −1 s −1 .

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Novel Gate-All-Around Poly-Si TFTs With Multiple Nanowire Channels

Cited by 52 publications

References 20 publications

Improving the Gate-Induced Drain Leakage and On-State Current of Fin-Like Thin Film Transistors with a Wide Drain

Improving the Gate-Induced Drain Leakage and On-State Current of Fin-Like Thin Film Transistors with a Wide Drain

Enhancement of programming speed on gate-all-around poly-silicon nanowire nonvolatile memory using self-aligned NiSi Schottky barrier source/drain

High-Performance Single-Crystal-Like Strained-Silicon Nanowire Thin-Film Transistors via Continuous-Wave Laser Crystallization

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