High-performance polycrystalline-silicon nanowire (NW) thin-film transistors (TFTs) have been demonstrated via continuous-wave laser crystallization (CLC) to exhibit the low subthreshold swing of 216 mV/decade and high ON/OFF ratio of 1.6×10 9 . In addition, the thermal stress of ∼800 MPa induced from the CLC process also contributed to the single-crystal-like silicon NW CLC TFTs to achieve an excellent field-effect mobility of up to 900 cm 2 V −1 s −1 .
In this work, a novel gate-all-around (GAA) low-temperature poly-Si (LTPS) junctionless (JL) silicon-oxide-nitride-oxide-silicon (SONOS) nonvolatile memory device with a field-enhanced nanowire (NW) structure has been proposed to improve the programing/erasing (P/E) performance. Each nanowire has three sharp corners fabricated by a sidewall spacer formation technique to obtain high local electrical fields. Owing to the higher carrier concentration in the channel and the high local electrical field from the three sharp corners, such a JL SONOS memory device exhibits a significantly enhanced P/E speed, a larger memory window, and better data retention properties than a conventional inversion mode NW-channel memory device.
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