2018 IEEE 2nd Electron Devices Technology and Manufacturing Conference (EDTM) 2018
DOI: 10.1109/edtm.2018.8421469
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Non-Universal Temperature Dependence of Hot Carrier Degradation (HCD) in FinFET: New Observations and Physical Understandings

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Cited by 15 publications
(12 citation statements)
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“…This has led to a general trend for very large-scale integration (VLSI) chips to increase in thermal design power at every generation, with notable deviations from this trend usually coming in the form of vast architectural improvements or splitting the die into multiple logical cores. The increase in dissipated heat is problematic for VLSI semiconductor chips because their functionality can unacceptably alter at high temperatures, due for instance to hot carrier degradation and bias temperature instability [4][5][6]. Now that devices are manufactured in the sub-10-nanometer process, it is becoming more difficult to manage waste heat production due to ever more important factors such as leakage current and Joule heating in interconnect circuit elements of decreasing cross-sectional area.…”
Section: Introductionmentioning
confidence: 99%
“…This has led to a general trend for very large-scale integration (VLSI) chips to increase in thermal design power at every generation, with notable deviations from this trend usually coming in the form of vast architectural improvements or splitting the die into multiple logical cores. The increase in dissipated heat is problematic for VLSI semiconductor chips because their functionality can unacceptably alter at high temperatures, due for instance to hot carrier degradation and bias temperature instability [4][5][6]. Now that devices are manufactured in the sub-10-nanometer process, it is becoming more difficult to manage waste heat production due to ever more important factors such as leakage current and Joule heating in interconnect circuit elements of decreasing cross-sectional area.…”
Section: Introductionmentioning
confidence: 99%
“…Therefore, some scientists started to model the traps rather than the increasingly complex carrier transport process [29]. A trap-based compact model is proposed, which is unified across different V gs /V ds regions with different carrier-based mechanisms [29][30][31]72,73]. For devices with different geometrical structure and crystal lattice, the trap types as well as their influence on device parameters may be different, thus it is needed to model them separately for different devices.…”
Section: Trap-based Hci Modelmentioning
confidence: 99%
“…Carrier-carrier interactions are considered to populate the high energetic tail of the carrier spectrum [14,[16][17][18][19] -i.e., accelerate HCD -and the rate of this process is an increasing function of T . However, recent findings have demonstrated that the temperature dependence of HCD is nonuniversal and is determined by the device geometry and stress conditions [20][21][22]. In particular Grill et al [22] have shown that the same device can show both acceleration and inhibition of HCD with growing T , depending on applied drain and gate voltages (V ds and V gs , respectively).…”
Section: Introductionmentioning
confidence: 99%