The impact of self-heating and its implications on hot-carrier degradation – A modeling study

Tyaginov, Stanislav; Makarov, Alexander; Chasin, Adrian; Bury, E.; Vandemaele, Michiel; Jech, Markus; Grill, Alexander; Keersgieter, A. De; Linten, Dimitri; Kaczer, B.

doi:10.1016/j.microrel.2021.114156

Cited by 8 publications

(4 citation statements)

References 76 publications

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“…This can be explained by the contribution of HCD under single particle (SP) at medium V GS and under multiple particle (MP) degradation at larger V GS [13], which may involve self-heating when V GS ≥ V DS [14,21]. Recent works have shown that the contribution of secondary holes generated by II leads to additional HCD effect in high voltage (HV) devices [22][23][24]. In this case, the SP (hot carriers) and MP (cold carriers) degradation mechanisms induce a cumulative effect showing that cold holes take a significant role in damaged high-voltage LDMOS [25].…”

Section: Worst Case DC Degradation In N-edmosmentioning

confidence: 99%

“…Accurate lifetime determination is known to be strongly dependent on the involved mechanisms in the device under operation [22][23][24][25][26] when one damage takes the lead, or several damages compete in parallel as a function of time. This is typically encountered between Off mode (V GS = 0) and On-mode, whereas some damage may dominate for a short time and the others over the long term [8][9][10][11].…”

Section: Quasi-static Lifetime Extractionmentioning

confidence: 99%

See 1 more Smart Citation

Hot-Carrier Damage in N-Channel EDMOS Used in Single Photon Avalanche Diode Cell through Quasi-Static Modeling

Bravaix,

Pitard,

Federspiel

et al. 2024

Micromachines

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A single photon avalanche diode (SPAD) cell using N-channel extended-drain metal oxide semiconductor (N-EDMOS) is tested for its hot-carrier damage (HCD) resistance. The stressing gate-voltage (VGS) dependence is compared to hot-hole (HH) injection, positive bias temperature (PBT) instability and off-mode (VGS = 0). The goal was to check an accurate device lifetime extraction using accelerated DC to AC stressing by applying the quasi-static (QS) lifetime technique. N-EDMOS device is devoted to 3D bonding with CMOS imagers obtained by an optimized process with an effective gate-length Leff = 0.25 µm and a SiO2 gate-oxide thickness Tox = 5 nm. The operating frequency is 10 MHz at maximum supply voltage VDDmax = 5.5 V. TCAD simulations are used to determine the real voltage and timing configurations for the device in a mixed structure of the SPAD cell. AC device lifetime is obtained using worst-case DC accelerating degradation, which is transferred by QS technique to the AC waveforms applied to N-EDMOS device. This allows us to accurately obtain the AC device lifetime as a function of the delay and load for a fixed pulse shape. It shows the predominance of the high energy hot-carriers involved in the first substrate current peak during transients.

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Section: Worst Case DC Degradation In N-edmosmentioning

confidence: 99%

Section: Quasi-static Lifetime Extractionmentioning

confidence: 99%

Hot-Carrier Damage in N-Channel EDMOS Used in Single Photon Avalanche Diode Cell through Quasi-Static Modeling

Bravaix,

Pitard,

Federspiel

et al. 2024

Micromachines

View full text Add to dashboard Cite

show abstract

“…However, the DD approach to the Boltzmann transport equation (BTE) solution is known to fail to model carrier transport in ultra-scaled FETs [40,41]. Therefore, implementation of the contribution of secondary carriers should rely on refined carrier transport treatment for both primary and secondary carriers [42]. The extended CPM is validated here against HCD data over a broad {V gs ,V ds } range.…”

Section: Introductionmentioning

confidence: 99%

Compact Physics Hot-Carrier Degradation Model Valid over a Wide Bias Range

Tyaginov,

Bury,

Grill

et al. 2023

Micromachines

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We develop a compact physics model for hot-carrier degradation (HCD) that is valid over a wide range of gate and drain voltages (Vgs and Vds, respectively). Special attention is paid to the contribution of secondary carriers (generated by impact ionization) to HCD, which was shown to be significant under stress conditions with low Vgs and relatively high Vds. Implementation of this contribution is based on refined modeling of carrier transport for both primary and secondary carriers. To validate the model, we employ foundry-quality n-channel transistors and a broad range of stress voltages {Vgs,Vds}.

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“…To understand this complex behavior we extend our HCD-SH model, which was verified to capture HCD data in pchannel NWFETs [31], to cover HCD in n-channel FinFETs.…”

Section: Introductionmentioning

confidence: 99%

Understanding and Modeling Opposite Impacts of Self-Heating on Hot-Carrier Degradation in n- and p-Channel Transistors

Tyaginov

Makarov²,

El-Sayed

et al. 2022

2022 IEEE International Reliability Physics Symposium (IRPS)

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We extend our framework for hot-carrier degradation (HCD) modeling by covering the impact of self-heating (SH) on HCD. This impact is threefold: (i) perturbation of carrier transport, (ii) acceleration of the thermal contribution to the Si-H bond breakage process, and (iii) and shortening vibrational lifetime of the bond resulting in reducing the multiple-carrier mechanism rate. We validate the framework against HCD data acquired on n-channel fin field-effect-transistors (FETs) and pchannel nanowire (NW) FETs under various stress conditions and analyze the importance of each of the aforementioned components of the SH impact on HCD. This analysis shows that in n-channel devices SH depopulates the high energetical fraction of the carrier distribution, while in p-channel transistors SH slightly shifts the carrier energy distribution towards higher energy. Thus, in nFinFETs the impact of SH on the carrier transport and enhancement of the thermal component of bond rupture compensate each other (vibrational lifetime shortening has a weak impact on HCD), thereby leading to slight inhibition of HCD by SH. To the contrary, in pNWFETs these two factors both enhance HCD (while the contribution of the vibrational lifetime dependence on temperature is again small) and thus SH accelerates HCD. Our modeling framework, therefore, can explain why in n-channel FETs SH slightly inhibits HCD, while in p-channel devices HCD is accelerated by SH.

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The impact of self-heating and its implications on hot-carrier degradation – A modeling study

Cited by 8 publications

References 76 publications

Hot-Carrier Damage in N-Channel EDMOS Used in Single Photon Avalanche Diode Cell through Quasi-Static Modeling

Hot-Carrier Damage in N-Channel EDMOS Used in Single Photon Avalanche Diode Cell through Quasi-Static Modeling

Compact Physics Hot-Carrier Degradation Model Valid over a Wide Bias Range

Understanding and Modeling Opposite Impacts of Self-Heating on Hot-Carrier Degradation in n- and p-Channel Transistors

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