Non-floating and low-power adiabatic logic circuit

Abstract

This paper proposes a new adiabatic logic. Adiabatic logic is a good method to reduce power consumption. Several common adiabatic logics suffer from floating output which results in lack in robustness, by using the periodic power supply. At first, we analyze the floating phenomenon of previously proposed 2PC2AL in this paper. The proposed adiabatic logic can prevent the floating of the nodes to add two logic switches between the power supply and charging-discharging transistor. This paper also reports a comparison of energy dissipation between the different adiabatic logics such as, ECRL, 2N2N2P, 2PASCL, 2PC2AL, and the proposed circuit. In the SPICE simulation, the target application is a 4-bit multiplier for IoT products. Through the simulation, the output of the proposed circuit with cascade connection has a stable function.

Analysis of Adiabatic Hybrid Full Adder and 32-Bit Adders for Portable Mobile Applications

“…A full adder is a combinational circuit which performs the arithmetic sum of three bits A, B and carry in from a previous addition and produces the corresponding SUM and CARRY out [24]. The Boolean expressions for sum and carry respectively are Sum =…”

“…The main drawback of this type of implementation is that sum circuit and carry circuit are implemented separately; due to this the critical path delay is more, more design complexity. Full voltage swing cannot be achieved by this circuits, and hence cascading will be limited to few stages [24].…”