Noise reduction techniques for an ECL-CMOS RAM with a 2 ns write cycle time

Ohhata, Kenichi; Sakurai, Yasuhisa; Nambu, H.; Kanetani, K.; Idei, Y.; Hiramoto, Toshiro; Tamba, N.; Yamaguchi, K.; Odaka, M.; Watanabe, Keiji; Ikeda, Takahide; Homma, N.

doi:10.1109/bipol.1992.274057

Cited by 4 publications

(4 citation statements)

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“…A number of solutions, such as BL twisting, have been proposed to reduce cross talk noise and increase the signal-noise ratio (SNR) [Ohhata92,Noda01]. These solutions, however, focus mainly on overcoming BL coupling from a design point of view, in order to prevent data destruction during a write operation [Takeda00], or in order to reduce the BL delay time during the precharge cycle, thereby increasing overall memory performance [Nambu95].…”

Section: Effects Of Couplingmentioning

confidence: 99%

Evaluation of SRAM faulty behavior under bit line coupling

Al-Ars

Hamdioui

2008

2008 3rd International Design and Test Workshop

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The faulty behavior of memory devices has traditionally been evaluated in isolation of the parasitic effects present on chip. As these effects become more dominant, however, they start to negatively influence the fault coverage of commonly used memory tests. This paper studies the way bit line coupling affects the faulty behavior of SRAM devices. Spice simulations are used to show how coupling can prevent the detection of otherwise detectable faults. Furthermore, an evaluation is done of the needed bit line coupling conditions to guarantee a high fault coverage of a given defect. This is done by identifying the most stressful data background patterns in the neighborhood of the faulty cell.

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Section: Effects Of Couplingmentioning

confidence: 99%

Evaluation of SRAM faulty behavior under bit line coupling

Al-Ars

Hamdioui

2008

2008 3rd International Design and Test Workshop

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“…With the decreasing of the transistor operating voltage, the threshold voltage is decreasing as well. The subthreshold current is computed as (5) where and are the gate width and drain current, respectively. is the subthreshold swing parameter, which can be calculated as (6) where is thermal voltage and is the junction capactance between source and drain.…”

Section: A Current Analysis Of Dual-transistorsmentioning

confidence: 99%

“…However, Itoh's results were obtained mainly from simulations rather than real chip measurement. Ohhata et al [5] and Horiuchi et al [6] have proposed various schemes to solve the bitline oscillation problem. Their works demand either special bipolar/SOI processes or capacitors within the circuit which will consume large area.…”

Section: Introductionmentioning

confidence: 99%

An sram design using dual threshold voltage transistors and low-power quenchers

Wang

Lee

Chen

2003

IEEE J. Solid-State Circuits

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Static random access memories (SRAM) are widely used in computer systems and many portable devices. In this paper, we propose an SRAM cell with dual threshold voltage transistors. Low threshold voltage transistors are mainly used in driving bitlines while high threshold voltage transistors are used in latching data voltages. The advantages of dual threshold voltage transistors can be used to reduce the access time and maintain data retention at the same time. Also, the unwanted oscillation of the output bitlines of memories caused by large currents in bitlines is reduced by adding two back-to-back quenchers. The proposed quenchers not only prevent oscillation, but also reduce the idle power consumption when the memory cells are not activated by wordline signals. Meanwhile, a large noise margin is provided such that the gain of the sense amplifier will not be reduced to avoid the oscillation. Hence, high-speed and low-power readout operations of the SRAMs are feasible.

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“…In fact, BL coupling and the resulting crosstalk noise is strongly considered as a limiting factor in designing high speed, low power SRAM devices [5]. Research on the impact of parasitic capacitance on the faulty behavior has up till now addressed faults in peripheral memory circuits as well as address decoders [14].A number of solutions, such as BL twisting, have been proposed to reduce cross talk noise and increase the signal-to-noise ratio [7], [8]. However, such solutions focus mainly on overcoming BL coupling from a design perspective and are expensive to implement making them infeasible in many applications [9], [6].…”

Section: Introductionmentioning

confidence: 99%

Bit line coupling memory tests for single-cell fails in SRAMs

Irobi

Al-Ars

Hamdioui

2010

2010 28th VLSI Test Symposium (VTS)

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Due to the decreasing dimensions of manufactured devices, the effect of bit line capacitive coupling on the behavior of faulty memory cells cannot be ignored. Neighboring cells influence the faulty behavior of defective cells through coupling. This paper analyzes and validates this behavior theoretically and through electrical simulations. The paper evaluates the impact of bit line coupling in SRAMs on cell faulty behavior and identifies necessary conditions to induce worst-case coupling effects.We present a test that guarantees detecting all singlecell static faults in the presence of capacitive coupling and worst-case neighborhood data for any possible open defect.

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Noise reduction techniques for an ECL-CMOS RAM with a 2 ns write cycle time

Cited by 4 publications

References 0 publications

Evaluation of SRAM faulty behavior under bit line coupling

Evaluation of SRAM faulty behavior under bit line coupling

An sram design using dual threshold voltage transistors and low-power quenchers

Bit line coupling memory tests for single-cell fails in SRAMs

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