An sram design using dual threshold voltage transistors and low-power quenchers

Wang, Chua-Chin; Lee, Po-Ming; Chen, Kuo-Long

doi:10.1109/jssc.2003.817254

Cited by 11 publications

(3 citation statements)

References 12 publications

(8 reference statements)

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“…The stronger pull-down CNTFET improves the RSNM as is also seen in the C6T SRAM designs. Also, the use of lower V th to drive the BL increases the read driving capability and RSNM at the same time [45]. The RSNM of the suggested SRAM is slightly reduced in comparison to BLP8T and LP8T which is compensated by the lower read delay shown by the suggested SRAM.…”

Section: Rsnm Analysismentioning

confidence: 92%

Design analysis of a low-power, high-speed 8 T SRAM cell using dual-threshold CNTFETs

Haq,

Abbasian,

Khurshid

et al. 2024

Phys. Scr.

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Recently, carbon nanotube field-effect transistors (CNTFETs) have garnered significant attention from VLSI engineers due to their exceptional electrical properties. This paper proposes a novel high-speed, low-power eight-transistor (8 T) static random-access memory (SRAM) cell based on 32-nm CNTFET technology. The SRAM cell was simulated using the HSPICE tool with a VDD of 0.9 V. The high-speed and low-power characteristics of the SRAM design are attributed to the high subthreshold slope and high carrier mobility of metal-oxide-semiconductor field-effect transistor (MOSFET)-like CNTFETs utilized in the simulations. The implementation of dual threshold transistors, coupled with a transmission gate for bitline access, contributes to the enhanced performance. Key performance metrics such as noise margins, power consumption, delay, and SRAM electrical quality metric (SEQM) of the proposed SRAM have been evaluated and compared with existing CNTFET-based SRAM designs. The proposed cell demonstrates reductions of 73.73%, 43.18%, and 58.70% in read power, write power, and hold power, respectively, compared to the lowest respective power values of other examined SRAM designs. The proposed SRAM ranks second, third, and second in write static noise margin (WSNM), hold static noise margin (HSNM), and read static noise margin (RSNM), respectively, among other designs. Additionally, the proposed SRAM exhibits the least sensitivity to parametric variations compared to other designs. The SEQM, which provides a comprehensive assessment of access times, noise margins, and power usage for the SRAM cell, has been calculated. The SEQM of the proposed SRAM is 10.6, 1.89, 13.15, and 1.82 times higher than that of C6T, BLP8T, Mani’s 10 T, and LP8T, respectively.

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Section: Rsnm Analysismentioning

confidence: 92%

Design analysis of a low-power, high-speed 8 T SRAM cell using dual-threshold CNTFETs

Haq,

Abbasian,

Khurshid

et al. 2024

Phys. Scr.

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“…2) transistors N1, N2, P1, P2 are designed as high threshold voltage (Vtn-high for NMOS, Vtp-high for PMOS) transistors because they are more appropriate to store data in memory design and access transistors N3, N4 are designed as low threshold voltage (Vtn) transistors because they can possess larger drain current. In result it reduces the access time and maintains data retention at the same time [20]- [27].…”

Section: Sram Cellsmentioning

confidence: 99%

“…Due to the higher number of transistor used in 7T SRAM cell its leakage energy consumption increases. To reduce the leakage current in 7T SRAM dual-threshold voltage technology [20]- [27] has been used. High-threshold voltage transistors are not used for the access transistor as it increases the write delay.…”

Section: Figmentioning

confidence: 99%

A Comparative Study of Single- and Dual-Threshold Voltage SRAM Cells

Kushwaha,

Chaudhry

2011

JTIT

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In this paper, a comparison has been drawn between 5 transistor (5T), 6T and 7T SRAM cells. All the cells have been designed using both single-threshold (conventional) and dual-threshold (dual-Vt) voltage techniques. Their respective delays and power consumption have been calculated at 180 nm and 65 nm CMOS technology. With technology scaling, power consumption decreases by 80% to 90%, with some increase in write time because of the utilization of high- Vt transistors in write critical path. The results show that the read delay of 7T SRAM cell is 9% lesser than 5T SRAM cell and 29% lesser than 6T SRAM cell due to the lower resistance of the read access delay path. While read power of 5T SRAM cell is reduced by 10% and 24% as compared to 7T SRAM, 6T SRAM cell respectively. The write speed, however, is degraded by 1% to 3% with the 7T and 5T SRAM cells as compared to the 6T SRAM cells due to the utilization of single ended architecture. While write power of 5T SRAM cell is reduced by up to 40% and 67% as compared to 7T SRAM, 6T SRAM cell respectively.

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