Bit line coupling memory tests for single-cell fails in SRAMs

Irobi, Sandra; Al-Ars, Zaid; Hamdioui, Said

doi:10.1109/vts.2010.5469624

Cited by 5 publications

(6 citation statements)

References 17 publications

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“…Generally, the bit line parasitic capacitance can be divided into three types of parasitic capacitances: (i) metal-wire capacitance of the bit lines, (ii) gate-to-drain overlap capacitance, and (iii) junction capacitance of the source and drain of the pass-gate transistors [17]. The metal-wire capacitance of the bit lines is a combination of (1) the capacitances between the BL and BL' metal wires, (2) the capacitance between the bit line and the other bit lines of neighboring SRAM cells, and (3) the capacitance between the bit line and the ground line (or GND, in short) [18]. The metal-wire capacitance of the bit line exists because there is always a capacitance between two metal wires or plates.…”

Section: Read Operationmentioning

confidence: 99%

Applications in Static Random Access Memory (SRAM)

Shin

2016

Variation-Aware Advanced CMOS Devices and SRAM

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Continuous efforts to shrink the physical size of transistors enable the integration of a larger number of transistors on a single chip. Today, it is feasible to fabricate a single SRAM cell in a 0.04999-µm 2 area [1]. However, as the transistors are aggressively scaled down, the impacts of the process-induced random variations on the device performance are dramatically increased [2]. The term "process-induced random variations" indicates that the process/fabrication steps such as doping, lithography, etching, chemical mechanical polishing (CMP), and so on, induce these random variations [3]. The well-known random variation sources caused by the aforementioned process steps are random dopant fluctuations (RDF) [4] [also known as random dopant distributions (RDD)] [5], line edge roughness (LER) [6], work function variations (WFV) [7] (also known as metal grain granularity (MGG) [8]), and oxide thickness variations [9]. Aforementioned random variations cause variations in parameters such as effective channel length and threshold voltage of each transistor. Then, the mismatches in the effective channel lengths and threshold voltages between two neighboring transistors cause degradations in the stability of the SRAM cells, which consist of a few transistors (e.g., 6 transistors for 6T SRAM cell) [10]. This is because each transistor of a single SRAM cell should be balanced in order to make it stable for the read/write/retention operations [11]. Further detailed information about how to balance the different transistors of a single SRAM cell, and how badly the stabilities of the SRAM cells are degraded by process-induced variations, will be provided later.Since random variations significantly affect the performance of SRAM cells, it is irrefutable that random variations are one of the key factors in the SRAM cell design. Furthermore, it is important to look for "random variation"-tolerant SRAM designs because random variations cannot be controlled, as systematic variations are controlled [12]. In order to find the random-variation-tolerant SRAM cell designs, understanding how the SRAM cell operates and how the process-induced

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Section: Read Operationmentioning

confidence: 99%

Applications in Static Random Access Memory (SRAM)

Shin

2016

Variation-Aware Advanced CMOS Devices and SRAM

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“…Figure 1. SRAM electrical Spice model [4] [5] Considering the read operation, it has been shown in [3][4] [5] that the coupling capacitance Cb causes neighboring BLs to have an influence on the voltage development only when reading from a cell. This effect can impact the proper sense amplifier operation, which results in an incorrect read data (while the stored value is still correct).…”

Section: Modeling Of Bit Line Coupling Capacitancesmentioning

confidence: 99%

“…Only opens within the cells have been considered in [4]. Opens located at BLs and WLs have not been considered.…”

Section: B Spot Defectsmentioning

confidence: 99%

“…This effect has an impact on the behavior of a memory cell, named victim cell, depending on its content and the content of the neighboring cells [4].…”

Section: Introductionmentioning

confidence: 99%

“…In [4], authors present a test algorithm, March SSSc, with a 12N complexity, where N is the number of memory cells in the memory. It guarantees the detection of all single-cell static faults both in presence and in absence of CC BL for any possible open defect.…”

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Optimized march test flow for detecting memory faults in SRAM devices under bit line coupling

Zordan

Bosio

Dilillo

et al. 2011

14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems

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A comprehensive SRAM test must guarantee the correct functioning of each cell of the memory (ability to store and to maintain data), and the corresponding addressing, write and read operations. SRAM testing is mainly based on the concept of fault model used to mimic faulty behaviors. Traditionally, the effects of bit line coupling capacitances have not been considered during the fault analysis. However, recent works show the increasing impact of bit line coupling capacitances on the SRAM behavior. This paper reviews and discusses preview works addressing the issues coming from bit line parasitic capacitances and data contents on SRAM testing, pointing out the impacts of these effects on the existing test solutions. Then, we introduce two optimizations of the state-ofthe-art test solution able to take into account the influence of bit line coupling capacitances while reducing the test length of about 60% and 80%, respectively.

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