Optimized march test flow for detecting memory faults in SRAM devices under bit line coupling

Abstract

A comprehensive SRAM test must guarantee the correct functioning of each cell of the memory (ability to store and to maintain data), and the corresponding addressing, write and read operations. SRAM testing is mainly based on the concept of fault model used to mimic faulty behaviors. Traditionally, the effects of bit line coupling capacitances have not been considered during the fault analysis. However, recent works show the increasing impact of bit line coupling capacitances on the SRAM behavior. This paper reviews and discusses preview works addressing the issues coming from bit line parasitic capacitances and data contents on SRAM testing, pointing out the impacts of these effects on the existing test solutions. Then, we introduce two optimizations of the state-ofthe-art test solution able to take into account the influence of bit line coupling capacitances while reducing the test length of about 60% and 80%, respectively.

Linked Coupling Faults Detection by Multirun March Tests

“…Various modifications of the March LR and March LA tests are effectively used to detect dynamic unlinked faults [15], test dynamic memory (DRAM) [16], and implement memory built-in self-tests (BISTs) [17,18]. Specific march tests, such as March SS, March BLC-Opt, March SR, March MSS, and March m-MSS, are applied to cover bit-line coupling faults [19][20][21] and their diagnoses by applying March Cd [22].…”

“…Multiple (multirun) memory testing was considered within the exhaustive, pseudo-exhaustive, and transparent memory testing frameworks [3,23]. In all cases, it was necessary to repeat the march test for various scenarios determined by the degrees of freedom inherent in march tests [20]. March memory tests detect complex faults by applying them repeatedly for various address sequences or initial memory cell states [31].…”