Memory Test Optimization for Parasitic Bit Line Coupling in SRAMs

FPGA memory testing technique using BIST

“…Also, variations in other device parameters, such as variations in wafer size, gate oxide thickness, channel length, feature size, capacitive coupling among signals, and power lines have a huge impact on the memory cell and other parts of memory. Recently, it has been proven that the Bit line coupling capacitance (CC BL ) develops undesired voltage coupling on adjacent memory cells belonging to the same world line, which can have an impact on the sense amplifier operation when reading data from the SRAM [1].…”

“…To address the above mentioned faults the current research uses a Built-in Self Test (BIST) technique for testing the SRAM memories in a Xilinx Virtex-4 series FPGA. In the field of FPGAs, BIST has been a topic of research and development for the past decade [1][2][3][4][5][6][7][8]. The BIST technique employs a Test Pattern Generator (TPG) which generates the input test pattern to test the Circuit Under Test (CUT).…”

“…However, the effects of read faults such as Deceptive Read Destructive and Data Retention Faults are ignored. In [1], a March test BLC of a 46n complexity is presented to detect all static faults caused by CC BL . Despite the effectiveness of March BLC, its time complexity is still high.…”