FPGA memory testing technique using BIST

Abstract

The wide use of Field Programmable Gate Arrays (FPGAs) in critical applications including, military and airborne applications require fault free operation of the FPGA. In FPGAs, faults can occur in the memory resources, logic blocks, or the interconnects. In this paper, memory faults including Stuck-at, Transition, Address Decoder, Incorrect Read, Deceptive Read Destructive, and Data Retention Faults are analyzed using an optimized March C-algorithm. In order to evaluate the effectiveness of this algorithm, a novel Built-in Self Test (BIST) technique to test the embedded SRAM memory of the FPGA is proposed. The proposed technique reduces the test time by approximately half as compared to previously published schemes. The FPGA is modeled in VHDL at the equivalent gate level and the simulations results are generated using ModelSim.

Low Power March Memory Test Algorithm for Static Random Access Memories

“…There by devices performance may be degraded or it may totally fail. Test time also high in traditional memory test techniques [9]. There are some methods proposed to reduce test power by reducing switching activity in test vectors [10].…”