Noise analysis using on-chip waveform monitor in bandgap voltage references

Murata, Akitaka; Agatsuma, Shuji; Ikoma, Daisaku; Ichikawa, Kouji; Tsuda, T.; Nagata, Makoto; Yoshikawa, Kumpei; Araga, Yuuki; Harada, Yuji

doi:10.1109/emccompo.2013.6735205

Cited by 6 publications

(1 citation statement)

References 9 publications

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“…In the present setup, V and T are set to be 100 μV and 100 ps, respectively, which determine the resolution of waveform capturing. The waveform acquisition algorithm associated with the OCM circuits has been explored [30], [31] and utilized for the in-place waveform-based evaluation of undesired noise coupling in automotive IC chips [32], [33]. Here, our MCM demonstrator adopts this technique in a customized way to evaluate the powering and signaling within the FO interposer featuring stacked membrane layers and proximate LSCs.…”

Section: An External Clock Generator Provides the System Clock Throug...mentioning

confidence: 99%

In-Place Evaluation of Powering and Signaling Within Fan-Out Multiple IC Chip Packaging

Sonoda

Kasai

Tanaka

et al. 2022

IEEE Trans. Compon., Packag. Manufact. Technol.

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This article confirms the advantage of fan-out (FO) packaging in the electrical performance of power delivery among integrated circuit (IC) chips with the best use of land side capacitors (LSCs). On-chip in-place waveform measurements quantitatively evaluate the integrity of powering and signaling within FO wafer level packaging (FOWLP) multiple chip module (MCM) demonstrators, where a pair of IC chips are assembled with LSCs with different sizes and structures. The IC chip incorporates an array of 12 digital cores and on-chip waveform monitor (OCM) circuits. Each digital core consists of a low-voltage differential signaling (LVDS) transceiver channel that is backed by a static random access memory (SRAM)-based builtin self test (BIST) module and supplied by an on-chip voltage regulator module (VRM). The LSCs are placed on the bottom side of an FO interposer and inserted between the output of VRM and the ground plane almost ideally with the shortest length of physical traces. A Si membrane capacitor of 10 nF sustains the lowest power line impedance over the frequency range of 2.0 GHz more constantly than a multilayer ceramic counterpart, and attenuates the high-order harmonic frequency components to the clocking frequency at 750 MHz. The leverage of LSCs in powering also improves signaling and helps achieve the wider eye openings in LVDS channels. The implications are elaborated for the capacitor selections with respect to the physical types of capacitors, the size of capacitances, and the level of shares in power delivery among digital cores, all toward the higher level of integrity in powering and signaling in FOWLP MCMs.

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