In-Place Power Noise and Signal Waveform Measurements on LVDS Channels in Fan-Out Multiple IC Chip Packaging

Sonoda, Hiroki; Nagata, Makoto; Tanaka, Daichi; Murakami, Yoshihide; Mihara, Kyoshi; Makida, Kazuo; Kikuchi, Katsuya

doi:10.1109/emccompo.2019.8919926

Cited by 2 publications

(1 citation statement)

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“…Those are attributed naturally to the construction of 3DIC stacks with vertically distributed capacitors among power delivery networks (PDNs) [25], [26]. The benefits of embedded capacitors in FOWLP devices were also exhibited by monitoring power and signal waveforms [27], [28]. The implications with the different property of interposers have been relevantly discussed with the same device architecture but integrated on a Si passive interposer differently from the fan-out one, which should be referred to [29].…”

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confidence: 99%

In-Place Evaluation of Powering and Signaling Within Fan-Out Multiple IC Chip Packaging

Sonoda

Kasai

Tanaka

et al. 2022

IEEE Trans. Compon., Packag. Manufact. Technol.

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This article confirms the advantage of fan-out (FO) packaging in the electrical performance of power delivery among integrated circuit (IC) chips with the best use of land side capacitors (LSCs). On-chip in-place waveform measurements quantitatively evaluate the integrity of powering and signaling within FO wafer level packaging (FOWLP) multiple chip module (MCM) demonstrators, where a pair of IC chips are assembled with LSCs with different sizes and structures. The IC chip incorporates an array of 12 digital cores and on-chip waveform monitor (OCM) circuits. Each digital core consists of a low-voltage differential signaling (LVDS) transceiver channel that is backed by a static random access memory (SRAM)-based builtin self test (BIST) module and supplied by an on-chip voltage regulator module (VRM). The LSCs are placed on the bottom side of an FO interposer and inserted between the output of VRM and the ground plane almost ideally with the shortest length of physical traces. A Si membrane capacitor of 10 nF sustains the lowest power line impedance over the frequency range of 2.0 GHz more constantly than a multilayer ceramic counterpart, and attenuates the high-order harmonic frequency components to the clocking frequency at 750 MHz. The leverage of LSCs in powering also improves signaling and helps achieve the wider eye openings in LVDS channels. The implications are elaborated for the capacitor selections with respect to the physical types of capacitors, the size of capacitances, and the level of shares in power delivery among digital cores, all toward the higher level of integrity in powering and signaling in FOWLP MCMs.

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