Nitrogen profile engineering in the interfacial SiON for HfAlOx gate dielectric

Mitsuhashi, Riichiro; Torii, Kazuyoshi; Ohji, Hiroshi; Kawahara, T.; Horiuchi, Atsushi; Takada, Hitoshi; Takahashi, Masashi; Kitajima, Hiroshi

doi:10.7567/ssdm.2004.b-1-3

Cited by 5 publications

(3 citation statements)

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“…16 Nitrogen incorporation in the interfacial layer helps it function as a barrier to both Si and O diffusion and is effective in reducing the equivalent oxide thickness ͑EOT͒. [17][18][19] Moreover, the nitrogen content in the interfacial layer should prevent degradation of the mobility with Hf-aluminate gate dielectrics. 19 In this study, we investigated the effect of the nitrogen concentration of the interfacial SiON layer on the electrical properties of MOSFETs, in which 0.5-nm-thick Hf-silicate/HfO 2 gate dielectrics were deposited using Hf͓N͑CH 3 ͒͑C 2 H 5 ͔͒ 4 and SiH͓N͑CH 3 ͒ 2 ͔ 3 precursors.…”

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confidence: 99%

Impact of Interface Layer Nitrogen Concentration on HfO[sub 2]∕Hf-Silicate/Poly-Si–Based MOSFET Performance

Kamiyama¹,

Miura²,

Nara³

2005

J. Electrochem. Soc.

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We fabricated metal oxide semiconductor field effect transistor ͑MOSFETs͒ with 0.5-nm-thick Hf-silicate/HfO 2 gate dielectrics on SiON base layers of different nitrogen concentration and studied the effects of the nitrogen concentration on their electrical properties. The gate dielectrics were deposited by atomic layer deposition ͑ALD͒ technology using Hf͓N͑CH 3 ͒͑C 2 H 5 ͔͒ 4 and SiH͓N͑CH 3 ͒ 2 ͔ 3 precursors. O 3 was used as an oxidant. Rapid thermal annealing ͑RTA͒ in a NO ambient gave rise to a SiON layer with a nitrogen concentration of about 7 atom %. With a NH 3 + NO ambient, the nitrogen concentration increased to 16%. Ultrathin films with equivalent oxide thickness ͑EOT͒ of about 1.0 nm could be fabricated using Hf-silicate/HfO 2 gate stacks on base layers of SiON. The leakage current density of devices with SiON base layers was about 1 order of magnitude less than that with a SiO 2 base layer, and that increased about 100 times for every 0.4-nm decrease of EOT. The flatband voltage ͑V FB ͒ and the threshold ͑V th ͒ with SiON base layers were slightly lower than those with a SiO 2 base layer, which implies that positive charge is generated due to nitrogen at the interface. The effective mobility for devices with Hf-silicate/HfO 2 gate stacks on SiON base layers was less than those with a SiO 2 base layer due to the higher interface trap density ͑N it ͒. Moreover, increasing the nitrogen concentration in the base layer led to an increase in the interfacial trap density, thereby decreasing the effective mobility.For many years, silicon dioxide ͑SiO 2 ͒ films have been the gate dielectric in complementary metal oxide semiconductor ͑CMOS͒ devices. For a gate oxide thickness of less than 3.5 nm, direct tunneling current increases 100 times for every 0.4-0.5 nm decrease of thickness. 1,2 This high gate leakage current would increase standby power consumption. In order to reduce the leakage current by direct tunneling, the high-dielectric-constant ͑high-k͒ materials allow for an increase in the physical thickness to maintain a low equivalent oxide thickness. Among many high-k materials, Hf-based and its nitride films are good for low leakage current and high carrier mobility. Therefore, sputter and/or metallorganic chemical vapor deposition ͑MOCVD͒ methods are currently used for the high-k film formation. [3][4][5][6][7][8][9] Atomic layer deposition ͑ALD͒ technology is desirable for precise control of composition, film thickness, conformality, and uniformity among many high-k film deposition techniques. [10][11][12][13][14][15] Hafnium-tetrachloride ͑HfCl 4 ͒ and water ͑H 2 O͒ were widely used for ALD HfO 2 film formations. [10][11][12] Recently, there were reports using Hf-amide-type precursors such as Hf͓N͑CH 3 ͒͑C 2 H 5 ͔͒ 4 for ALD of HfO 2 or Hf-aluminate films to solve the problem of particle formation with HfCl 4 precursors. 13-15 Furthermore, when ALD HfO 2 films were deposited at low temperature ͑around 300°C͒ using Hf͓N͑CH 3 ͒ 2 ͔ 4 precursor and O 3 as the oxidant instead of H 2 O, those films conta...

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confidence: 99%

Impact of Interface Layer Nitrogen Concentration on HfO[sub 2]∕Hf-Silicate/Poly-Si–Based MOSFET Performance

Kamiyama¹,

Miura²,

Nara³

2005

J. Electrochem. Soc.

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“…Moreover, excess nitridation of Hf-silicates causes the shift of V th to be higher in pMIS due to the positive charge of Si-N bond, and also the mobility reduction. Therefore, the nitrogen should be placed at far from silicon substrate (12). These were problems to the development of cMIS devices.…”

Section: Introductionmentioning

confidence: 99%

High Performance Gate-First pMISFET with TiN/HfSiON Gate Stacks Fabricated with PVD-Based In-Situ Method

Kawahara¹,

Nishida²,

Sakashita³

et al. 2007

ECS Trans.

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We could obtain high performance gate-first pMISFET with TiN/HfSiON gate stacks fabricated with PVD-based in-situ method. High-quality Hf silicate gate dielectrics were formed by utilizing a solid phase interface reaction (SPIR) between a metal Hf layer and an SiO 2 underlayer, and TiN electrodes were continuously grown on the gate dielectrics using a low-damage sputtering system without exposure to air. Sufficiently high effective work function (WF = ~ 4.8eV) of the TiN electrodes was achieved after activation annealing at 1050ºC-spike. The in-situ process was found to be effective to reduce carbon impurity of the gate stacks and we could improve device performance, such as drive current I on , subthreshold swing S-value, and carrier mobility. I on = 350µA/µm at I off = 200pA/µm could be obtained, which was a 13% improvement over ex-situ CVD-TiN on CVD-HfSiON. Moreover, this PVD-based in-situ method with moderate fluorine ion implantation into the substrate would reduce the threshold voltage V th even more without deterioration of I on .

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“…5) In order to overcome this difficulty, an ultra-thin SiON interfacial layer with precise nitrogen profile control is required. 6) Although hafnium silicate (HfSiO x ) or nitrided hafnium silicate (HfSiON) provide a wider process window, precise control of oxygen and nitrogen profiles is required in the integration of nitridation and in the thermal process. 1) In contrast, in ''gate-last'' MISFETs, for example, ''damascene'' or ''replacement'' MISFET, PDA temperature and the thermal budget after the high-k gate dielectric film deposition in the fabrication process of MISFETs are not restricted by the activation annealing temperature but by the silicide thermal stability on S/D.…”

Section: Introductionmentioning

confidence: 99%

Area-Selective Post-Deposition Annealing Process Using Flash Lamp and Si Photoenergy Absorber for Metal/High-k Gate Metal–Insulator–Semiconductor Field-Effect Transistors with NiSi Source/Drain

Matsuki¹,

Nishimura²,

Akasaka³

et al. 2006

jjap

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We have proposed an area-selective post-deposition annealing (PDA) process that involves a combination of flash lamp annealing and the use of a Si photoenergy absorber (Si-PEA) for metal/high-k gate last metal-insulator-semiconductor fieldeffect transistors (MISFETs) with NiSi on source/drain (S/D). The process makes it possible to suppress the increase in both the sheet resistance and junction leakage current of NiSi S/D regions. This PDA process also showed optimality for silicide gate electrode formation with silicidation of part of the Si-PEA. It was found that the flash lamp PDA with Si-PEA on nickelsilicide/HfAlO x /SiO 2 gate-last MISFETs reduced electron trapping at the gate dielectric and resulted in better PBTI immunity than conventional rapid thermal PDA and flash lamp PDA without Si-PEA.

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Nitrogen profile engineering in the interfacial SiON for HfAlOx gate dielectric

Cited by 5 publications

References 0 publications

Impact of Interface Layer Nitrogen Concentration on HfO[sub 2]∕Hf-Silicate/Poly-Si–Based MOSFET Performance

Impact of Interface Layer Nitrogen Concentration on HfO[sub 2]∕Hf-Silicate/Poly-Si–Based MOSFET Performance

High Performance Gate-First pMISFET with TiN/HfSiON Gate Stacks Fabricated with PVD-Based In-Situ Method

Area-Selective Post-Deposition Annealing Process Using Flash Lamp and Si Photoenergy Absorber for Metal/High-k Gate Metal–Insulator–Semiconductor Field-Effect Transistors with NiSi Source/Drain

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