New technologies for advanced high density 3D packaging by using TSV process

Abstract

There is no question that 3D integration will be the next generation of packaging. This requires new technologies from ultra thin wafer handling to wafer to wafer bonding with 3D inter substrate connections.TSV is a process in which wafers are thinned, stacked and interconnected to significantly improve electrical performance such as signal transmission, interconnect density, reduced power consumption, form factor and manufacturing costs. TSV -the next generation of packaging Graph 2: comparison wire bonding to 3D stackingThe TSV process requires ultra thin wafers with less than 50µm to reduce the stack thickness and improve the performance of the IC Device. EVG has developed a solution for temporary bonding of wafers to carriers to be able to run in standard IC Fab's all processes for back grinding, etching, metallization, wafer bonding and solder ball formation. Ultra thin wafer handling solutionsDepending on the process requirements 2 different solutions are on the market: -lamination of tapes on carriers, Si or glass wafers; disadvantage of tapes are the limitation of process temperature of usually max 170°C as well as the poor edge protection -spin on adhesive materials on carriers with the advantage of high process temperature up to 250°C with excellent edge protection. Graph 3: edge protection by tape versa spin on materialEVG has developed systems for a fully automated lamination and bond process as well as de-bonding systems for high volume manufacturing.When high process temperature e.g. for metallization is required we prefer spin on materials from our partner Brewer Science. The materials from Brewer Science HT250 and HT10.10 have high chemical resistance as well as high thermal resistance up to 250°C.

Fabrication and Optimization of High Aspect Ratio Through-Silicon-Vias Electroplating for 3D Inductor

“…With the requirements of reduced feature size and increased transistor performance for semiconductor technology, three-dimensional (3D) integration technology—using through-silicon-vias (TSVs) to realize the interconnection of multi-stacked chips—has emerged as a promising technology [ 1 , 2 , 3 , 4 ]. 3D integration technology can produce shorter interconnections in the vertical direction, resulting in a faster response and better performance of integrated circuits (ICs).…”

Research on a 3D Encapsulation Technique for Capacitive MEMS Sensors Based on Through Silicon Via

“…Therefore, choosing a suitable packaging solution is significant in order to obtain better performance and lower costs. The 3D wafer-level packaging technology, combined with a wafer bonding and vertical interconnection technique, has great potential in realizing a smaller size, lower power consumption, and lower fabrication cost [2,3,4,5,6]. Due to the fact that Pyrex glass has a similar coefficient of thermal expansion (CTE) to silicon, the anodic bonding between silicon and glass is usually applied to the hermetic packaging for MEMS devices to obtain high packaging reliability.…”

3D surface mounting

“…Those crystals have spherical, column-like or elastic pins on all surfaces [9], [10]. The most advanced approach to increase density is the package-on-package mounting with through-silicon via (TSV) [11], [12]. That is the typical mounting technique in stacked-die and package-in-package microsystems.…”