New low complexity bidirectional systolic structures for serial multiplication over the finite field GF(qm)

High-throughput hardware-efficient digit-serial architecture for field multiplication over GF(2^m)

“…It consists of three combinational sections: the modular reduction section, the AND section and the addition section. The modular reduction section consists of eight modular reduction cells [shown in Fig.2(b)] for w = 8, where the i-th modular reduction cell performs i number of XOR operations according to (10) in parallel to produce [z i .A j (z) mod Q(z)] during the j-th cycle. The i-th modular reduction cell consists of i number of 2-input XOR gates to perform the i number of XOR operations of (10) in parallel.…”

“…The bit-serial architectures on the other hand may be opted for implementation of ECC in highly constrained systems, but these architectures cannot be used for high-speed applications due to their low throughput rates. To double the throughput rate without proportionate increase in hardware, a bidirectional data-flow scheme is used in semisystolic designs for serial-parallel multipliers [10]. But the structures of [10] involve substantially large area due to the additional storage registers in the basic cells.…”

“…To double the throughput rate without proportionate increase in hardware, a bidirectional data-flow scheme is used in semisystolic designs for serial-parallel multipliers [10]. But the structures of [10] involve substantially large area due to the additional storage registers in the basic cells. In [11] also a bidirectional serial-parallel design is suggested, where the field multiplication is carried out in two separate linear systolic arrays.…”

Two systolic architectures for multiplication in GF (2m)

“…The`summing ®rst' designs perform the addition ®rst and then covert the sum into SBR form. Within this category, Wang et al [7] implemented AB in a straightforward way, Wei [8] implemented AB 2 C, Guo et al [9] used a high-radix implementation for computing AB, and Mekhallalati et al [10] slightly modi®ed the systolic architecture in a semi-systolic array by applying a re-timing process to reduce the initial delay. Conversely, the`modulus ®rst' designs convert both the addend and the augend into SBR form ®rst and then perform the addition.…”

Fast Hardware Implementations of Inversions in Small Finite Fields for Special Irreducible Polynomials on FPGAs

“…Among finite field arithmetic, multiplications and inversions have been received continuous attentions. Efficient implementations of such arithmetic in finite fields are essential, e.g., multiplication [1][2][3][4][5][6][7][8][9][10], inversion [11][12][13][14][15][16][17][18][19][20][21][22][23][24][25][26][27][28][29][30] and division [31][32][33][34][35][36][37][38]. More and more designs and implementations of multiplications, inversions and divisions in finite fields have been proposed.…”