Fast Hardware Implementations of Inversions in Small Finite Fields for Special Irreducible Polynomials on FPGAs

Yi, Haibo; Li, Weijian; Nie, Zhe

doi:10.14257/ijsia.2016.10.9.12

Cited by 4 publications

(3 citation statements)

References 27 publications

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“…The number of clock cycle for Hex ITA is given by the Eq. (11). It includes 5 clock cycle for pre-computation and 1 clock cycle for final squaring and 2L (L-length of addition chain) clock cycles for multiplications and remaining for hex operation.…”

Section: Hex Itoh-tsujii Algorithm (Hita)mentioning

confidence: 99%

“…Among different arithmetic operation, FF inversion is one of the most important and computationally complex operations. Several attempts have been made to fasten the inverse operation [3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22] using squarer and quad circuits on FPGA platforms. There are two useful approaches for finding an inversion over GF (2 m ) which includes Extended Euclidean Algorithm (EEA) [14,23] and Fermat's Little Theorem (FLT) [24].…”

Section: Introductionmentioning

confidence: 99%

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A Hex Itoh-Tsujii inversion algorithm for FPGA platforms

Kalaiarasi¹,

Venkatasubramani²,

Rajaram³

2021

IEICE Electron. Express

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The Itoh-Tsujii inversion algorithm forms a major contribution in finding the inverse in cryptographic applications such as Elliptic Curve Cryptography. In this paper, a new Hex Itoh-Tsujii inversion algorithm is proposed to compute the multiplicative inverse efficiently on Field-Programmable Gate-arrays (FPGA) platforms for binary fields generated by NIST recommended irreducible trinomials. The Hex Itoh Tsujii inversion Algorithm based proposed architecture is constructed with hex circuits and quad addition chain. This combination improves the resource utilization. The experimental results shows that the proposed work has better Area-Time Performance compared with the existing implementation.

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Section: Hex Itoh-tsujii Algorithm (Hita)mentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

A Hex Itoh-Tsujii inversion algorithm for FPGA platforms

Kalaiarasi¹,

Venkatasubramani²,

Rajaram³

2021

IEICE Electron. Express

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show abstract

“…Introduction. Finite field operations have gained increasing importance due to the fact that they are fundamental operations frequently encountered in areas of mathematic [1,5,23,26,27,29,[36][37][38] and engineering [4,7,16,28]. Generally, operations are computed via using a specific basis [2,3,6,9,10,13,[19][20][21][22]25,32,34,35], i.e.…”

mentioning

confidence: 99%

Efficient systolic multiplications in composite fields for cryptographic systems

Yi¹

2019

Discrete &Amp; Continuous Dynamical Systems - S

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Multiplications in finite fields are playing a key role in areas of cryptography and mathematic. We present approaches to exploit systolic architecture for multiplications in composite fields, which are expected to reduce the time-area product substantially. We design a pipelined architecture for multiplications in composite fields GF ((2 n) 2), where n is a positive integer. Besides, we design systolic architectures for multiplications and additions in finite fields GF (2 n). By integrating main improvements and other minor optimizations for multiplications in GF ((2 n) 2), the non-pipelined versions of our design takes 8n + 4 AND gates and 8n XOR gates to compute multiplications with the executing time of nT AN D + 4nT XOR , where T AN D and T XOR are delays of AND and XOR gates respectively; with the aid of pipelining, the pipelined version of our design has a throughput rate of one result per 2nT XOR. Other words, the time complexity and area complexity of our design are O(n). Thus, the complexity of time-area product of our design is O(n 2). Experimental results and comparisons show that our design provides significant reductions in executing time and area of multiplications. 2010 Mathematics Subject Classification. 12Y05.

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Towards Wearability in Cryptographic Systems: A Novel Architecture Based on Rainbow Scheme for Wearable Devices

2017

Wireless Pers Commun

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Fast Hardware Implementations of Inversions in Small Finite Fields for Special Irreducible Polynomials on FPGAs

Abstract: Abstract

Cited by 4 publications

References 27 publications

A Hex Itoh-Tsujii inversion algorithm for FPGA platforms

A Hex Itoh-Tsujii inversion algorithm for FPGA platforms

Efficient systolic multiplications in composite fields for cryptographic systems

Towards Wearability in Cryptographic Systems: A Novel Architecture Based on Rainbow Scheme for Wearable Devices

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