A Hex Itoh-Tsujii inversion algorithm for FPGA platforms

Kalaiarasi, M.; Venkatasubramani, V. R.; Rajaram, S.

doi:10.1587/elex.18.20210108

Cited by 4 publications

(1 citation statement)

References 28 publications

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“…The most recent FPGA implementations of BHC model, using a pipelined approach, are presented in [10], [22], [23]. Multiplication and inversion are performed with the leastsignificant-digit level approach and Itoh-Tsujii inversion algorithm [24] respectively. The work in [22] is dedicated to the BHC model only whereas the work in [23] presents a flexible solution.…”

Section: A Related Workmentioning

confidence: 99%

An Optimized Architecture for Binary Huff Curves With Improved Security

et al. 2021

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In order to compute the elliptic curve point addition and doubling, the unified point addition law provides better protection against side channel attacks. One of the elliptic curve models, providing the unified point addition, is Binary Huff Curves (BHC). Recently, a new unified method for BHC with improved security against side channel attacks, has been proposed. Therefore, an optimized hardware architecture in terms of higher clock frequency and throughput for the new unified point addition method is required. Consequently, this article has three major contributions: The first contribution is to modify the unified addition law from hardware implementation point of view, resulting 31% decrease in memory requirements. The second contribution is the analysis of memory optimized unified law in the context of pipelining. In this regard, this article proposes an instruction scheduling policy for a 2-stage pipelined architecture which provides 36% reduction in the number of required clock cycles, 14.3% improvement in clock frequency, 53.2% decrease in computation time and 54.5% improvement in throughput/area. Finally, the third contribution is to propose a 4-stage pipelined architecture. The proposed 4-stage pipelined architecture provides an additional 19% improvement in clock frequency and 10% increase in throughput, as compared to the 2-stage pipelined architecture.

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