High-throughput hardware-efficient digit-serial architecture for field multiplication over GF(2&lt;sup&gt;m&lt;/sup&gt;)

Meher, Pramod Kumar

doi:10.1109/icics.2007.4449560

Cited by 13 publications

(3 citation statements)

References 17 publications

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“…Clock is used as input in this modified kogge stone multiplier using ZFL. The below figure (7) shows the output waveform of modified kogge stone multiplier using ZFL.…”

Section: Fig 4 Block Diagram Of Modified Kogge Stone Multiplier Using Zflmentioning

confidence: 99%

Design of High Speed and Area efficient modified Kogge Stone Multiplier Using ZFL

Fariddin¹,

Mishra²

2021

Proceedings of the First International Conference on Computing, Communication and Control System, I3CAC 2021, 7-8 June 2021, Bh

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In the applications of digital signal processing, multipliers plays important role. Basically, Finite field multiplier is the easiest of all operations in the finite field and most frequently used operation in arithmetic's. Hence in this paper the design of high speed and area efficient modified kogge stone multiplier is implemented. Multiplier and multiplicand are taken as input in this system. From both multiplier and multiplicand 1's and 0's are identified. Factoring technique is utilized to minimize switching energy and increase the speed of operation. Zeros finding logic will identify the zeros from obtained product. This product will be added using parallel prefix adder to minimize the area. Compared to ripple carry multiplier, kogge stone multiplier, the proposed kogge stone multiplier gives effective results.

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“…Clock is used as input in this modified kogge stone multiplier using ZFL. The below figure (7) shows the output waveform of modified kogge stone multiplier using ZFL.…”

Section: Fig 4 Block Diagram Of Modified Kogge Stone Multiplier Using Zflmentioning

confidence: 99%

Design of High Speed and Area efficient modified Kogge Stone Multiplier Using ZFL

Fariddin¹,

Mishra²

2021

Proceedings of the First International Conference on Computing, Communication and Control System, I3CAC 2021, 7-8 June 2021, Bh

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show abstract

“…If L is the cyclic-left-shift operation and the product word in (4) can then be expressed equivalently as (12)…”

Section: Types Of Pipelinementioning

confidence: 99%

Novel Pipelined Scalable Systolic Multiplier Based on Irreducible All-One Polynomials

2019

IJITEE

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A planned productive structure issued for the systolic execution of authoritative based limited field duplication over G F(2 m) in light of final 56-bit AOP is proposed in this work. We extricated a recursive increase calculation and utilized it to plan an intermittent and confined piece level reliance outline (DG) for systolic registering. The intermittent piece level DG is changed into a very smal grained DG, and the pipe coating is utilized for snappier mapping into a parallel systolic design. It doesn't require any overall correspondences for measured decline, in contrast to most current developments. The suggested bit-parallel systolic structure is similar to the parallel systolic structure, however the quantity of registers is altogether lower.

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“…The input operands are partitioned into digits of certain number of bits and fed in digit-by-digit in digit-serial systolic designs. The output is also obtained digit-bydigit in successive cycles [4]. In serial/parallel structures, the bits of one of the operands are fed in parallel, the other input operand is fed either in bit-serial or in digit-serial manner and the output is obtained in parallel [5].…”

Section: Introductionmentioning

confidence: 99%

Fault Tolerant Techniques for Finite Field Multipliers

Sargunam

Dhanasekaran

2014

AMM

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The use of finite field multipliers in the critical applications like elliptic curve cryptography needs Concurrent Error Detection (CED) and correction at architectural level to provide high reliability. This paper discusses fault tolerant technique for polynomial representation based finite field multipliers. The detection and correction are done on-line. We use a combination of Double Modular Redundancy (DMR) and Concurrent Error Detection (CED) techniques. The fault tolerant finite field multiplier is coded in VHDL and simulated using Modelsim. Further, the proposed multiplier with fault tolerant capability is synthesized and results are analyzed with respect to area occupied, input and output pin counts and delay. Our technique, when compared with existing techniques, gives better performance. We show that our concurrent error detecting multiplier over GF(2m) requires less than 200% extra hardware, whereas with the traditional fault tolerant techniques, such as Triple Modular Redundancy (TMR), overhead is more than 200%.

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High-throughput hardware-efficient digit-serial architecture for field multiplication over GF(2<sup>m</sup>)

Cited by 13 publications

References 17 publications

Design of High Speed and Area efficient modified Kogge Stone Multiplier Using ZFL

Design of High Speed and Area efficient modified Kogge Stone Multiplier Using ZFL

Novel Pipelined Scalable Systolic Multiplier Based on Irreducible All-One Polynomials

Fault Tolerant Techniques for Finite Field Multipliers

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