The wireless sensor networks (WSNs) with dynamic topology communication among the sensor nodes is vulnerable to numerous attacks. As they have limited power, there arises a conflict between the complex security scheme and the consumption of energy which are inversely proportional to each other. Hence, a trade-off should be accomplished between the implemented scheme and energy. A novel secure and energy-aware routing technique quantized indexive energy-aware clustering-based combinatorial stochastic sampled bat optimization (QIEAC-CSSBO) is proposed which consists of clustering, optimal route path identification, and route maintenance. The clustering process and selection of cluster head (CH) with high residual energy is done using the quantized Schutz indexive Linde–Buzo–Gray algorithm (QIEAC). Optimal route identification is done using CSSBO (combinatorial stochastic sampled Prevosti’s bat optimization), and fitness of every bat is measured on combinatorial functions, namely, distance, energy, trust, and link stability among nodes. Stochastic universal sampling selection procedure is applied to select the global best optimal path for secure data transmission. Lastly, route maintenance process is performed to identify alternative route while link failure occurs among nodes. Experimental assessment is performed using various performance metrics, namely, energy consumption, packet delivery ratio, packet drop rate, throughput, and delay. The proposed method QIEAC-CSSBO enhances the performance of packet delivery ratio by 4%, throughput by 26%, and packet drop rate by 27% and reduces energy consumption by 11%, as well as delay by 16% as compared to existing techniques.
Multipliers are the obligatory component in most of the Digital Signal Processing applications. Designing high speed and low area multipliers are of substantial research interest. For attaining high speed, the Wallace high-speed multiplier utilizing Wallace tree adders are used predominantly. This paper puts forward the design and implementation of high performance Fused Add-Multiply (FAM) unit constituting 4:2 compressor block. The conventional FAM unit using Modified Booth (MB) multiplier incorporating Wallace tree structure with 3:2 compressor suffered by its performance limitations such as high latency and hardware complexity. The speed of traditional Wallace tree structure can be enhanced by employing 4:2 compressor in the FAM design and it attempts to minimize the stage delays of a conventional design using 3:2 compressor. Therefore an area effective and speed optimized FAM unit is proposed to overcome the bottleneck of conventional design. The analysis of both existing and proposedtechniques are clearly manifested. FAM units are simulated using Modelsim SE 10.0b and implemented in FPGA using Xilinx ISE for performance analysis. Index Terms-Fused Add-Multiply (FAM) unit, 4:2 compressor, Wallace tree structure.
Finite field multipliers are widely used in the field of cryptography for the purpose of scalar multiplication. The outputs of the finite field multipliers may consist of errors due to certain natural radiations which further leads to the failure of the cryptosystems. Here two Concurrent Error Detection (CED) schemes namely time redundancy and modular inversion based error detection schemes for finite field multipliers are discussed. The CED techniques have been implemented for bit serial, digit serial and bit parallel Montgomery multipliers. The Simulation results are obtained using Modelsim10.0b, area and power analysis has been performed using Xilinx ISE 9.1i. The proposed modular inversion based CED scheme is found to be area and power efficient compared to existing time redundancy based CED scheme.
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