Two systolic architectures for multiplication in GF (2m)

Abstract

Two new systolic architectures are presented for multiplications in the ®nite ®eld GF(2 m). These two architectures are based on the standard basis representation. In Architecture-I, the authors attempt to speed up the operation by using a new partitioning scheme for the basic cell in a straightforward systolic architecture to shorten the clock cycle period. In Architecture-II, they eliminate the one clock cycle gap between iterations by pairing off the cells of Architecture-I. They compare their architectures with previously proposed systolic architectures and a semisystolic architecture, and show that their Architecture-I offers the highest speed and Architecture-II the lowest hardware complexity.

High-Radix Design of a Scalable Modular Multiplier

“…q Y is pre-computed before the computational cycle begins since it depends only on the least significant k bits of X. This observation leaves the computation of q M in the most critical part of the algorithm as it is also pointed out by other authors [13,20].…”

A systolic trinomial GF(2k) multiplier based on the Montgomery Multiplication Algorithm

“…The proposed Multiplier architecture requires k clock cycles to come up with a result (Latency) and employs k 2 AND Gates, k 2 XOR gates and k 2 Flip Flops needed for the pipelining. [8] 2k 2 2k 2 7k 2 3k T AND + T XOR Tsai [11] 2k 2 2k 2 8k 2 2k T AND + T XOR In Table 1, the proposed MM architecture is compared with other well known semisystolic architectures in terms of gate -flip flop number, latency and critical path. The proposed semisystolic Montgomery Multiplier architecture is very advantageous in terms of gate -flip flop number and latency and achieves slightly higher critical path when compared with the LSbit semisystolic architectures of [8], [11].…”

“…[8] 2k 2 2k 2 7k 2 3k T AND + T XOR Tsai [11] 2k 2 2k 2 8k 2 2k T AND + T XOR In Table 1, the proposed MM architecture is compared with other well known semisystolic architectures in terms of gate -flip flop number, latency and critical path. The proposed semisystolic Montgomery Multiplier architecture is very advantageous in terms of gate -flip flop number and latency and achieves slightly higher critical path when compared with the LSbit semisystolic architectures of [8], [11]. In comparison with the Montgomery multiplier architecture of [10] which uses general irreducible polynomial and the MMFF algorithm, the proposed Montgomery Multiplier architecture has slightly more AND Gates, approximately the same XOR gates but considerably less DFF and half the latency of [10].…”

A Low-Power Design for Reed–Solomon Decoders

“…4 to compute ∆ (i) or Ω i over GF (2 m ). 7 From the finite-field arithmetic, the multiplication of two operands can be split into Fig. 4.…”