A Low-Power Design for Reed–Solomon Decoders

Abstract

In this paper, a low-power design for the Reed–Solomon (RS) decoder is presented. Our approach includes a novel two-stage syndrome calculator that reduces the syndrome computations by one-half, a modified Berlekamp–Massey algorithm in the key equation solver and a terminated mechanism in the Chien search circuit. The test chip for (255,239) and (208,192) RS decoders are implemented by 0.25 μm CMOS 1P5M and 0.35 μm CMOS SPQM standard cells, respectively. Simulation results show our approach can work successfully and achieved large reduction of power consumption on the average.