New efficient design of digital comparator

Wang, GuangJie; Sheng, Shimin; Ji, Lijiu

doi:10.1109/icasic.1996.562803

Cited by 7 publications

(4 citation statements)

References 1 publication

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“…Some of the comparator designs use dynamic logic to achieve low-power consumption but limitations of low-speed and poor-noise margin make the dynamic design rather challenging. The other designs use subtractors in the form of flat adder components along with custom logic circuits [9][10][11][12][13] to implement comparison process for wider bit operands but these designs give slower response and area intensive arrangement [14][15][16]. The improvement in the scalability and reduction in the comparison delay has been achieved in hierarchical prefix tree structure-based comparator that composed of 2 bit comparators at each level [17].…”

Section: Introductionmentioning

confidence: 99%

High‐speed and area‐efficient scalable N ‐bit digital comparator

Tyagi

Pandey

2020

IET Circuits, Devices & Systems

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An area-efficient N-bit digital comparator with high operating speed and low-power dissipation is presented in this work. The proposed comparator structure consists of two separate modules. The first module is the comparison evaluation module (CEM) and the second module is the final module (FM). Independent from the input operand bitwidths, stages present in CEM involve the regular structure of repeated logic cells used for implementing parallel prefix tree structure. The FM validates the final comparison based on results obtained from the CEM. The presence of regular very large-scale integration topology in the proposed structure allows the analytical derivation of the area in terms of total number of transistors present in the design and total delay encountered in input-output flow as the function of input operand bitwidth. Spectre simulation results have been presented using 0.18 µm complementary metal-oxide-semiconductor (CMOS) technology at 1 GHz. The main advantages of the proposed comparator are minimum input-output delay of 0.57 ns, minimum fan-out-of-4 delay of 9.5 ns and low-power dissipation of 1.03 mw as compared with existing comparators designed using 180 nm CMOS technology for 64 bit comparison.

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Section: Introductionmentioning

confidence: 99%

High‐speed and area‐efficient scalable N ‐bit digital comparator

Tyagi

Pandey

2020

IET Circuits, Devices & Systems

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“…Multiplexer based comparator architectures a headed the design of comparator architectures that made use of adders. The multiplexer based comparators divide the n -bit input into two n/2 bits and the result of two n/2 comparators is fed to the multiplexer that provide the result of the comparison with un-optimized power consumption [9]- [13].The comparators are designed using All N Transistor (ANT) circuits, but all the NMOS transistors that are connected in series enter saturation mode during operation which increases over all conductive resistance [13]. Some uses priority encoder architectures.…”

Section: Introductionmentioning

confidence: 99%

CMOS based Power Efficient Digital Comparator with Parallel Prefix Tree Structure

Prasanna¹,

Sahiti²,

Raghuveera³

et al. 2018

IJET

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A 128-Bit Digital Comparator is designed with Digital Complementary Metal Oxide Semiconductor (CMOS) logic, with the use of Parallel Prefix Tree Structure [1] technique. The comparison is performed on Most Significant Bit (MSB) to the Least Significant Bit (LSB). The comparison for the lower order bits carried out only when the MSBs are equal. This technique results in Optimized Power consumption and improved speed of operation. To make the circuit regular, the design is made using only CMOS logic gates. Transmission gates were used in the existing design and are replaced with the simple AND gates. This 128-Bit comparator is designed using Cadence TSMC 0.18µm technology and optimized the Power dissipation to 0.28mW and with a Delay of 0.87μs.

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“…The design problem of binary comparators is examined in many articles. In [3], the comparator is offered to build like an adder by using of a generate function and a propagate function which can be realized by the Manchester carry chain.…”

Section: Introductionmentioning

confidence: 99%

Designing of Hierarchical Structures for Binary Comparators on FPGA/SoC

Salauyou

Gruszewski

2015

Computer Information Systems and Industrial Management

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Part 5: Modelling and OptimizationInternational audienceThe article considers the general synthesis technique of hierarchical tree structures on FPGA/SoC for binary comparators. Designing of first level comparators is given. The best hierarchical comparator structure for the specific FPGA/SoC family is found empirically by experimental researches. The offered method allows reducing an area from 5.3% to 43.0%, and for high bitwidth comparators (with an input word length 1024) by 2.225 times. In the conclusion additional opportunities of the offered method are marked, and main directions of further researches are presented

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New efficient design of digital comparator

Cited by 7 publications

References 1 publication

High‐speed and area‐efficient scalable N ‐bit digital comparator

High‐speed and area‐efficient scalable N ‐bit digital comparator

CMOS based Power Efficient Digital Comparator with Parallel Prefix Tree Structure

Designing of Hierarchical Structures for Binary Comparators on FPGA/SoC

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