High‐speed and area‐efficient scalable N ‐bit digital comparator

Abstract

An area-efficient N-bit digital comparator with high operating speed and low-power dissipation is presented in this work. The proposed comparator structure consists of two separate modules. The first module is the comparison evaluation module (CEM) and the second module is the final module (FM). Independent from the input operand bitwidths, stages present in CEM involve the regular structure of repeated logic cells used for implementing parallel prefix tree structure. The FM validates the final comparison based on results obtained from the CEM. The presence of regular very large-scale integration topology in the proposed structure allows the analytical derivation of the area in terms of total number of transistors present in the design and total delay encountered in input-output flow as the function of input operand bitwidth. Spectre simulation results have been presented using 0.18 µm complementary metal-oxide-semiconductor (CMOS) technology at 1 GHz. The main advantages of the proposed comparator are minimum input-output delay of 0.57 ns, minimum fan-out-of-4 delay of 9.5 ns and low-power dissipation of 1.03 mw as compared with existing comparators designed using 180 nm CMOS technology for 64 bit comparison.

Seismic communication data processing based on compressed sensing algorithm

“…Once the reconstructed data pass through the low‐pass filter, an analogue‐level signal can be obtained. The analogue‐level signal is then processed into a digital‐level signal using a comparer which marks the end of the shaping (Tyagi & Pandey, 2020). Using sampling judgement technology, seismic data are converted into numbers comprising 1 and 0 (Perla & Provost, 2012).…”

“…I G U R E 4The principle of using orthogonal matching pursuit (OMP) algorithms to restore seismic signals and generate text for broadcasting. signal using a comparer which marks the end of the shaping(Tyagi & Pandey, 2020). Using sampling judgement technology, seismic data are converted into numbers comprising 1 and 0(Perla & Provost, 2012).…”

Design of High Speed and Area Efficient N-Bit Digital Comparator

“…This novel EX-OR-NOR cell is based on pass transistor logic and CMOS logic and this logic has been considered from [3]. It consists of 7 transistors.…”

“…The area is analysed by estimating the total number of cells required in each set and the logic cells will be translated into total number of transistors [3]…”

“…In this paper we are designing the comparator which is efficient in terms of speed, power consumption and area. To improve the power consumption, we have used parallel prefix tree structure method, and to produce the full swing output voltage a novel EX-OR-NOR cell had been considered from [3]. DESIGN METHODOLOGY Let's consider 2 input operands A and B as shown in fig.…”