A Novel Design of Voltage and Temperature Resilient 9-T Domino Logic XOR /XNOR Cell

Sharma, Uma; Jhamb, Mansi

doi:10.1007/s00034-022-02085-5

Cited by 5 publications

(1 citation statement)

References 29 publications

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“…In this study, the design metric is evaluated using 2500 samples in order to increase accuracy. In this research article, Monte Carlo simulation has been performed to calculate the variability (σ/ μ) (the ratio of Standard Deviation (σ) to Mean(μ)) [34].…”

Section: Variability Analysis Of Proposed Designmentioning

confidence: 99%

Variability aware ultra-low power design of NOR/NAND gate using non-conventional techniques

Sharma,

Jhamb

2024

Eng. Res. Express

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Fundamental to digital signal processing applications such as the Arithmetic Logic Unit (ALU), logic gates serve as the foundational components. This paper presents NOR and NAND gates engineered for operation within the ultra-low voltage (LV) and low power domains (LP). Utilizing the floating gate MOSFET (FGMOS) approach, this study adopts a strategy to enhance performance, focusing on reducing design complexity and minimizing power consumption.The proposed FGMOS-NAND/NOR gate design is investigated for important device parameters such as power (pwr), delay (tp), power delay product (PDP), and energy delay product (EDP). At 0.7 V supply, the overall power consumption of the FGMOS NOR and NAND gates is 0.442nW and 0.323nW, respectively. Further, carbon nanotube field effect transistor (CNTFET) technology is used to implement NOR and NAND gates in this research work. A rigorous comparative analysis was conducted in this research study to assess the performance of non-conventional technologies, specifically field-effect transistors with floating gate (FGMOS) and carbon nanotube field-effect transistors (CNFET), in comparison to the conventional complementary metal-oxide-semiconductor (CMOS) technology. Notably, our investigation revealed that when carbon nanotube field-effect transistor (CNTFET) technology is synergistically employed in conjunction with FGMOS technology, the overall circuit performance is significantly enhanced. Furthermore, in order to estimate the robustness and reliability of the proposed designs, comprehensive analysis pertaining to delay and power-delay product (PDP) variability were meticulously carried out within the scope of this research article.

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Section: Variability Analysis Of Proposed Designmentioning

confidence: 99%