A 128-Bit Digital Comparator is designed with Digital Complementary Metal Oxide Semiconductor (CMOS) logic, with the use of Parallel Prefix Tree Structure [1] technique. The comparison is performed on Most Significant Bit (MSB) to the Least Significant Bit (LSB). The comparison for the lower order bits carried out only when the MSBs are equal. This technique results in Optimized Power consumption and improved speed of operation. To make the circuit regular, the design is made using only CMOS logic gates. Transmission gates were used in the existing design and are replaced with the simple AND gates. This 128-Bit comparator is designed using Cadence TSMC 0.18µm technology and optimized the Power dissipation to 0.28mW and with a Delay of 0.87μs.
The paper describes a voltage level shifter for power efficient applications which is simulated in tanner spice tool using 45nm technology. The conservative voltage level shifter is designed by using 6 transistors. The voltage level shifter cell generally used for shifting the voltage range of the signal from one voltage domain to another. This is required when the chip operate at multiple voltage domains. The circuit parameters like leakage voltage and average power dissipation are calculate for this circuit. Mainly level shifter consists of two voltage levels. One is low logic supply voltage (VDDL) another one is high logic supply voltage (VDDH). The simulation results of proposed level shifter with Wilson current mirror by 45nm technology for the input frequency of 1MHZ, the power dissipation of 0.177nW with 3db gain of 9.78.
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